TSL2581, TSL2583

LIGHT-TO-DIGITAL CONVERTER

TAOS134A − JULY 2012

14

r

r

Copyright

E 2012, TAOS Inc.

The LUMENOLOGY

r Company

www.taosinc.com

Interrupt Threshold Registers (03h − 06h)

The interrupt threshold registers store the values to be used as the high and low trigger points for the comparison

function for interrupt generation. If the value generated by channel 0 crosses below or is equal to the low

threshold specified, an interrupt is asserted on the interrupt pin. If the value generated by channel 0 crosses

above the high threshold specified, an interrupt is asserted on the interrupt pin. Registers TLLOW and

TLHIGH provide the low byte and high byte, respectively, of the lower interrupt threshold. Registers THLOW

and THHIGH provide the low and high bytes, respectively, of the upper interrupt threshold. The high and low

bytes from each set of registers are combined to form a 16-bit threshold value. The interrupt threshold registers

default to 00h on power up.

Table 9. Interrupt Threshold Registers

REGISTER

ADDRESS

BITS

DESCRIPTION

TLLOW

3h

7:0

ADC channel 0 lower byte of the low threshold

TLHIGH

4h

7:0

ADC channel 0 upper byte of the low threshold

THLOW

5h

7:0

ADC channel 0 lower byte of the high threshold

THHIGH

6h

7:0

ADC channel 0 upper byte of the high threshold

NOTE: Since two 8-bit values are combined for a single 16-bit value for each of the high and low interrupt thresholds, the Send Byte protocol should

not be used to write to these registers. Any values transferred by the Send Byte protocol with the MSB set would be interpreted as the

COMMAND field and stored as an address for subsequent read/write operations and not as the interrupt threshold information as desired.

The Write Word protocol should be used to write byte-paired registers. For example, the TLLOW and TLHIGH registers (as well as the

THLOW and THHIGH registers) can be written together to set the 16-bit ADC value in a single transaction.

Analog Register (07h)

The ANALOG register provides eight bits of control to the analog block. These bits control the analog gain

settings of the device.

Table 10. Analog Register

6

75

4

2

31

0

RESV

GAIN

Address

07h

Reset

00h

Bit :

FIELD

BITS

DESCRIPTION

Resv

7:3

Reserved. Write as 0.

Gain Control. Sets the analog gain of the device according to the following table.

FIELD VALUE

GAIN VALUE

Gain

2:0

x00

1

×

Gain

2:0

x01

8

×

x10

16

×

x11

111

×