TSL2581, TSL2583

LIGHT-TO-DIGITAL CONVERTER

TAOS134A − JULY 2012

12

r

r

Copyright

E 2012, TAOS Inc.

The LUMENOLOGY

r Company

www.taosinc.com

Interrupt Register (02h)

The INTERRUPT register controls the extensive interrupt capabilities of the device. The open-drain interrupt

Register provides control over when a meaningful interrupt will occur. The concept of meaningful change can

be defined by the user both in terms of light intensity and time, or persistence of that change in intensity. The

value must cross the threshold (as configured in the Threshold Registers 03h through 06h) and persist for some

period of time, as outlined in Table 8.

When a level Interrupt is selected, an interrupt is generated whenever the last conversion results in a value

outside of the programmed threshold window. The interrupt is active-low and remains asserted until cleared by

writing an 11 in the TRANSACTION field in the COMMAND register.

Note:

Interrupts are based on the value of Channel 0 only.

Table 6. Interrupt Control Register

6

75

4

2

31

0

INTR_STOP

Resv

Resv

PERSIST

Address

02h

Reset

00h

Bit :

INTR

FIELD

BITS

DESCRIPTION

Resv

7

Reserved. Write as 0.

INTR_STOP

6

Stop ADC integration on interrupt. When high, ADC integration will stop once an interrupt is asserted. To

resume operation (1) de-assert ADC_EN using CONTROL register, (2) clear interrupt using COMMAND

register, and (3) re-assert ADC_EN using CONTROL register. Note: Use this bit to isolate a particular

condition when the sensor is continuously integrating.

Resv

5

Reserved. Write as 0.

INTR

4

INTR Control Select. This field determines mode of interrupt logic according to Table 7, below.

PERSIST

3:0

Interrupt persistence. Controls rate of interrupts to the host processor as shown in Table 8, below.

Table 7. Interrupt Control Select

INTR FIELD VALUE

READ VALUE

0

Interrupt output disabled

1

Level Interrupt