Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

ATV2500BQL Datasheet(PDF) 9 Page - ATMEL Corporation

Part # ATV2500BQL
Description  High-Speed High-Density UV Erasable Programmable Logic Device
PDF  18 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

ATV2500BQL Datasheet(HTML) 9 Page - ATMEL Corporation

Back Button ATV2500BQL Datasheet HTML 5Page - ATMEL Corporation ATV2500BQL Datasheet HTML 6Page - ATMEL Corporation ATV2500BQL Datasheet HTML 7Page - ATMEL Corporation ATV2500BQL Datasheet HTML 8Page - ATMEL Corporation ATV2500BQL Datasheet HTML 9Page - ATMEL Corporation ATV2500BQL Datasheet HTML 10Page - ATMEL Corporation ATV2500BQL Datasheet HTML 11Page - ATMEL Corporation ATV2500BQL Datasheet HTML 12Page - ATMEL Corporation ATV2500BQL Datasheet HTML 13Page - ATMEL Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 9 / 18 page
background image
ATV2500B
9
AC Characteristics
Symbol
Parameter
-12
-15
-20
-25
-30
Units
Min
Max
Mi
n
Ma
x
Min
Ma
x
Min
Ma
x
Min
Ma
x
t
PD1
Input to Non-Registered Output
12
15
20
25
30
ns
t
PD2
Feedback to Non-Registered
Output
12
15
20
25
30
ns
t
PD3
Input to Non-Registered
Feedback
8
11
151820
ns
t
PD4
Feedback to Non-Registered
Feedback
8
11
151820
ns
t
EA1
Input to Output Enable
12
15
20
25
30
ns
t
ER1
Input to Output Disable
12
15
20
25
30
ns
t
EA2
Feedback to Output Enable
12
15
20
25
30
ns
t
ER2
Feedback to Output Disable
12
15
20
25
30
ns
t
AW
Asynchronous Reset Width
6
8
12
15
18
ns
t
AP
Asynchronous Reset to
Registered Output
15
18
22
28
30
ns
t
APF
Asynchronous Reset to
Registered Feedback
12
15
19
25
30
ns
Input Test Waveforms and
Measurement Levels
Output Test Load
Preload and Observability of Registered Outputs
The ATV2500Bs registers are provided with circuitry to
allow loading of each register asynchronously with either a
high or a low. This feature will simplify testing since any
state can be forced into the registers to control test
sequencing. A V
IH level on the odd I/O pins will force the
appropriate register high; a V
IL will force it low, independent
of the polarity or other configuration bit settings.
The PRELOAD state is entered by placing an 10.25V to
10.75V signal on SMP lead 42. When the preload clock
SMP lead 23 is pulsed high, the data on the I/O pins is
placed into the 12 registers chosen by the Q select and
even/odd select pins.
Register 2 observability mode is entered by placing an
10.25V to 10.75V signal on pin/lead 2. In this mode, the
contents of the buried register bank will appear on the
associated outputs when the OE control signals are active.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com