ATV2500BQL datasheet(10/18 Pages) ATMEL

10 / 18 page

ATV2500B

Power-Up Reset

The registers in the ATV2500Bs are designed to reset dur-

ing power up. At a point delayed slightly from V

CC crossing

RST, all registers will be reset to the low state. The output

state will depend on the polarity of the output buffer.

This feature is critical for state as nature of reset and the

uncertainty of how VCC actually rises in the system, the fol-

lowing conditions are required:

The V

CC rise must be monotonic,

After reset occurs, all input and feedback setup

times must be met before driving the clock pin or

terms high, and

The clock pin, and any signals from which clock

terms are derived, must remain stable during t

PR.

Level forced on

Odd I/O pin

during

PRELOAD cycle

Q Select Pin

State

Even/Odd Select

Even Q1 state

after cycle

Even Q2 state

after cycle

Odd Q1 state

after cycle

Odd Q2 state

after cycle

IH/VIL

Low

High/Low

IH/VIL

High

Low

High/Low

IH/VIL

Low

High

High/Low

IH/VIL

High

High/Low

Parameter

Description

Typ

Max

Units

Power-Up Reset Time

600

1000

RST

Power-Up Reset Voltage

3.8

4.5

ATV2500BQL Datasheet(PDF) 10 Page - ATMEL Corporation

ATV2500BQL Datasheet(HTML) 10 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Datasheet Download

Link URL