ATV2500B

5

Note:

1.

These diagrams show equivalent logic functions, not necessarily the actual circuit implementation.

Note:

1. These four terms are shared with D/T1.

Clock Option

S2 = 0

Terms in

Output Configuration

S1

S0

D/T1

D/T2

0084

Registered (Q1); Q2 FB

10

12

4

(1)

Registered (Q1); Q2 FB

1184

Registered (Q1); D/T2 FB

S3

Ouput Configuration

S6

Q1 CLOCK

0

Active Low

0

CK1

1

Active High

1

CK1 • PIN1

S4

Register 1 Type

S7

Q2 CLOCK

0D

0CK2

1T

1CK2 • PIN1

S5

Register 2 Type

0D

1T

S2 = 1

Terms in

Output Configuration

S5

S1

S0

D/T1

D/T2

X0

0

4

(1)

4

Combinatorial (8 Terms);

Q2 FB

X

0

144

Combinatorial (4 Terms);

Q2 FB

X1

0

4

(1)

4

(1)

Combinatorial (12 Terms);

Q2 FB

11

1

4

(1)

4

Combinatorial (8 Terms);

D/T2 FB

01

144

Combinatorial (4 Terms);

D/T2 FB