DS80C390 datasheet(7/58 Pages) DALLAS

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DS80C390

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110199

80C32 COMPATIBILITY

The DS80C390 is a CMOS 80C32-compatible microcontroller designed for high performance. Every

effort has been made to keep the core device familiar to 80C32 users while adding many new features.

Because the device runs the standard 8051 instruction set, in general software written for existing 80C32-

based systems will work on the DS80C390. The primary exceptions are related to timing-critical issues,

since the high-performance core of the microcontroller executes instructions much faster than the

original. Memory interfacing is performed identically to the standard 80C32. The high-speed nature of

the DS80C390 core will slightly change the interface timing, and designers are advised to consult the

timing diagrams in this data sheet for more information.

The DS80C390 provides the same timer/counter resources, full duplex serial port, 256 bytes of scratchpad

RAM and I/O ports as the standard 80C32.

Timers will default to a 12 clocks per machine cycle

operation to keep timing compatible with original 8051 systems, but can be programmed to run at the

faster 4 clocks per machine cycle if desired.

New hardware functions are accessed using Special

Function Registers that do not overlap with standard 80C32 locations.

This data sheet provides only a summary and overview of the DS80C390. Detailed descriptions are

available in the corresponding user’s guide. This data sheet assumes a familiarity with the architecture of

the standard 80C32. In addition to the basic features of that device, the DS80C390 incorporates many

new features.

PERFORMANCE OVERVIEW

The DS80C390’s higher performance comes not just from increasing the clock frequency, but from a

more efficient design.

This updated core removes the dummy memory cycles that are present in a

standard, 12 clocks per machine cycle 8051. In the DS80C390, the same machine cycle takes 4 clocks.

Thus the fastest instruction, 1 machine cycle, executes 3 times faster for the same crystal frequency. The

majority of instructions on the DS80C390 will see the full 3 to 1 speed improvement, while a few will

execute between 1.5 and 2.4 times faster.

Regardless of specific performance improvements, all

instructions are faster than the original 8051.

Improvement of individual programs will depend on the actual mix of instructions used. Speed sensitive

applications should make the most use of instructions that are 3 times faster. However, the large number

of 3 to 1 improved opcodes makes dramatic speed improvements likely for any arbitrary combination of

instructions.

These architecture improvements and the sub-micron CMOS design produce a peak

instruction cycle in 100 ns (10 MIPs). The Dual Data Pointer feature also allows the user to eliminate

wasted instructions when moving blocks of memory.

INSTRUCTION SET SUMMARY

All instructions perform exactly the same functions as their 8051 counterparts. Their effect on bits, flags,

and other status functions is identical. However, the timing of instructions is different, both in absolute

and relative number of clocks. The absolute timing of software loops can be calculated using a table in

the user’s guide. However, counter/timers default to run at the traditional 12 clocks per increment. In

this way, timer-based events occur at the standard intervals with software executing at higher speed.

Timers optionally can run at the faster 4 clocks per increment to take advantage of faster processor

operation.

The relative time of two DS80C390 instructions might differ from the traditional 8051. For example, in

the original architecture the “MOVX A, @DPTR” instruction and the “MOV direct, direct” instruction

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