DS80C390 datasheet(12/58 Pages) DALLAS

12 / 58 page

DS80C390

12 of 58

110199

MEMORY ADDRESSING

The DS80C390 incorporates three internal memory areas:

§ 256 bytes of scratchpad (or direct) RAM

§ 4 KB of SRAM configurable as various combinations of MOVX data memory, stack memory, and

MOVC program memory

§ 512 bytes of RAM reserved for the CAN message centers.

Up to 4 MB of external memory is addressed via a multiplexed or demultiplexed 20-bit address bus/8-bit

data bus and four chip enable (active during program memory access) or four peripheral enable (active

during data memory access) signals.

Three different addressing modes are supported, as selected by the AM1, AM0 bits in the ACON SFR.

16-bit address mode

16-bit address mode accesses memory similarly to the traditional 8051. It is opcode compatible with the

8051 microprocessor and identical to the byte and cycle count of the Dallas Semiconductor High-Speed

Microcontroller family. A device operating in this mode can access up to 64 KB of program and data

memory. The device defaults to this mode following any reset.

22-bit paged address mode

The 22-bit paged address mode retains binary code compatibility with the 8051 instruction set, but adds

one machine cycle to the ACALL, LCALL, RET and RETI instructions with respect to the Dallas

Semiconductor High-Speed Microcontroller family timing.

This is transparent to standard 8051

compilers. Interrupt latency is also increased by one machine cycle. In this mode, interrupt vectors are

fetched from 0000xxh.

22-bit contiguous address mode

The 22-bit contiguous addressing mode uses a full 22-bit program counter, and all modified branching

instructions automatically save and restore the entire program counter. The 22-bit branching instructions

such as ACALL, AJMP, LCALL, LJMP, MOV DPTR, RET and RETI instructions require an assembler,

compiler and linker that specifically supports these features. The INC DPTR is lengthened by one cycle

but remains byte count compatible with the standard 8051 instruction set.

Internally, the device uses a 22-bit program counter. The lowest order 22 bits are used for memory

addressing, with a special 23

rd bit used to map the 4KB SRAM above the 4 MB memory space in

bootstrap loader applications.

Address bits 16-23 for the 22-bit addressing modes are generated via

additional SFRs dependent on the type of instruction as shown below.

EXTENDED ADDRESS GENERATION: Table 2

Address bits 23-16

Address bits 15-8

Address bits 7-0

MOVX instructions using DPTR

DPX;93h

DPH;83h

DPL;82h

MOVX instructions using DPTR1

DPX1;95h

DPH1;85h

DPL1;84h

MOVX instructions using @Ri

MXAX;EAh

P2;A0h

Addressing program memory in

22-bit paged mode

AP;9Ch

10-bit stack pointer mode

ESP;9Bh

SP;81h

DS80C390 Datasheet(PDF) 12 Page - Dallas Semiconductor

DS80C390 Datasheet(HTML) 12 Page - Dallas Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

Datasheet Download

Link URL