DS80C390 datasheet(14/58 Pages) DALLAS

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DS80C390

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110199

PROGRAM MEMORY CHIP ENABLE BOUNDARIES Table 7

P4CNT.5-3

CE0

CE1

CE2

CE3

000

0h-7FFFh

8000h-FFFFh

10000h-17FFFh

18000h-1FFFFh

100

0h-1FFFFh

20000h-3FFFFh

40000h-5FFFFh

60000h-7FFFFh

101

0h-3FFFFh

40000h-7FFFFh

80000h-BFFFFh

C0000h-FFFFFh

110

0h-7FFFFh

80000h-FFFFFh

100000h-17FFFFh 180000h-1FFFFFh

111(default)

0-FFFFFh

100000h-1FFFFFh

200000h-2FFFFFh 300000h-3FFFFFh

The DS80C390 incorporates a feature allowing PCE and CE signals to be combined. This is useful when

incorporating modifiable code memory as part of a bootstrap loader or for in-system reprogrammability.

Setting the

PDCE3

− (MCON.3-0) bits causes the corresponding chip enable signal to function for both

MOVC and MOVX operations. Write access to combined program and data memory blocks is controlled

by the WR signal, and read access is controlled by the PSEN signal. This feature is especially useful if

the design achieves in-system reprogrammability via external Flash memory, in which a single device is

accessed via both MOVC instructions (program fetch) and MOVX Write operations (updates to code

memory). In this case, the internal SRAM is placed in the program/data configuration and loaded with a

small bootstrap loader program stored in the external Flash memory.

The device then executes the

internal bootstrap loader routine to modify/update the program memory located in the external Flash

memory.

STRETCH MEMORY CYCLES

The DS80C390 allows user application software to select the number of machine cycles it takes to

execute a MOVX instruction, allowing access to both fast and slow off-chip data memory and/or

peripherals without glue logic. High-speed systems often include memory-mapped peripherals such as

LCDs or UARTs with slow access times, so it may not be necessary or desirable to access external

devices at full speed. The microprocessor can perform a MOVX instruction in as little as two machine

cycles or as many as twelve machine cycles. Accesses to internal MOVX SRAM always use two cycles.

Note that stretch cycle settings affect external MOVX memory operations only and that there is no way to

slow the accesses to program memory other than to use a slower crystal (or external clock).

External MOVX timing is governed by the selection of 0 to 7 Stretch cycles, controlled by the MD2-MD0

SFR bits in the Clock Control Register (CKCON.2-0). A Stretch of zero will result in a two-machine

cycle MOVX instruction. A Stretch of seven will result in a MOVX of twelve machine cycles. Software

can dynamically change the Stretch value depending on the particular memory or peripheral being

accessed.

The default of one Stretch cycle allows the use of commonly available SRAMs without

dramatically lengthening the memory access times.

Stretch cycle settings affect external MOVX timing in three gradations. Changing the Stretch value from

0 to 1 adds an additional clock cycle each to the data setup and hold times. When a Stretch value of 4 or

above is selected, the interface timing changes dramatically to allow for very slow peripherals. First, the

ALE signal is lengthened by 1 machine cycle. This increases the address setup time into the peripheral

by this amount. Next, the address is held on the bus for one additional machine cycle increasing the

address hold time by this amount. The WR and RD signals are then lengthened by a machine cycle.

Finally, during a MOVX write the data is held on the bus for one additional machine cycle, thereby

increasing the data hold time by this amount. For every Stretch value greater than 4, the setup and hold

times remain constant, and only the width of the read or write signal is increased. These three gradations

are reflected in the AC Electrical characteristics, where the eight MOVX timing specifications are

represented by only three timing diagrams.

DS80C390 Datasheet(PDF) 14 Page - Dallas Semiconductor

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