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DS80C390 Datasheet(PDF) 1 Page - Dallas Semiconductor |
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DS80C390 Datasheet(HTML) 1 Page - Dallas Semiconductor |
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1 / 58 page ![]() 1 of 58 110199 FEATURES § 80C52 compatible − 8051 instruction-set compatible − Four 8-bit I/O ports − Three 16-bit timer/counters − 256 bytes scratchpad RAM § High-Speed Architecture − 4 clocks/machine cycle (8051=12) − Runs DC to 40 MHz clock rates − Frequency multiplier reduces EMI − Single-cycle instruction in 100 ns − 16/32-bit math coprocessor § 4 kB internal SRAM usable as program/data/stack memory § Enhanced memory architecture − Addresses up to 4 MB external − Defaults to true 8051 memory compatibility − User-enabled 22-bit program/data counter − 16-Bit/22-bit paged/22-bit contiguous modes − User-selectable multiplexed / non- multiplexed memory interface − Optional 10 bit stack pointer § Two full-function CAN 2.0B controllers − 15 message centers per controller − Standard 11-bit or extended 29-bit identification modes − Supports DeviceNet, SDS, and higher layer CAN protocols − Disables transmitter during autobaud − SIESTA low power mode § Two full-duplex hardware serial ports § Programmable IrDA clock § High integration controller includes − Power-fail reset − Early-warning power-fail interrupt − Programmable watchdog timer − Oscillator-fail detection § 16 total interrupt sources with 6 external § Available in 64-pin QFP, 68-pin PLCC PIN ASSIGNMENT DS80C390 Dual CAN High-Speed Microprocessor www.dalsemi.com 64-PIN QFP PRELIMINARY 1 61 9 10 26 27 43 60 44 DS80C390 68-PIN PLCC 49 DS80C390 48 33 32 17 16 1 64 |
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