PD488588FF datasheet(63/79 Pages) ELPIDA

Part #	PD488588FF

Description	288M bits Direct Rambus DRAM for High Performance Solution

PDF	79 Pages

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Manufacturer	ELPIDA [Elpida Memory]

Direct Link	http://www.elpida.com/en

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63 / 79 page

Data Sheet

E0251N20 (Ver. 2.0)

µµµµPD488588FF-C80-40

The SCK clock is also used for sampling data on RSL input in one situation. Figure23-4 shows the PDN and NAP

exit sequences. If the PSX field of the INIT register is one (Figure 22-1 control registers (1/7) “INIT Register”), then

the PDN and NAP exit sequences are broadcast; i.e. all RDRAMs that are in PDN or NAP will perform the exit

sequence. If the PSX field of the INIT register is zero, then the PDN and NAP exit sequences are directed; i.e. only

one RDRAM that is in PDN or NAP will perform the exit sequence.

The address of that RDRAM is specified on the DQA[5:0] bus in the set hold window tS3/tH3 around the rising edge of

SCK. This is shown Figure 33-2. The SCK timing point is measured at the 50 % level, and the DQA [5:0] bus signals

are measured at the VREF level.

Figure 33-2 CMOS Timing - Device Address for NAP or PDN Exit

V IH,CMOS

80%

50%

20%

V IL,CMOS

SCK

PDEV

V DIH

80%

20%

VDIL

DQA[5:0]

tS3

tH3

REF

PD488588FF Datasheet(PDF) 63 Page - Elpida Memory