PD488588FF datasheet(34/79 Pages) ELPIDA

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Data Sheet

E0251N20 (Ver. 2.0)

µµµµPD488588FF-C80-40

21. Initialization

Figure 21-1 SIO Pin Reset Sequence

SCK

CMD

SIO0

T16

0000000000000000

00000000...00000000

0000000000000000

SIO1

The packet is repeated

from SIO0 to SIO1

00001100

Initialization refers to the process that a controller must go through after power is applied to the system or the system

is reset. The controller prepares the RDRAM sub-system for normal Channel operation by (primarily) using a

sequence of control register transactions on the serial CMOS pins. The following steps outline the sequence seen by

the various memory subsystem components (including the RDRAM components) during initialization. This sequence

is available in the form of reference code. Contact Rambus Inc. for more information.

1.0 Start Clocks

This step calculates the proper clock frequencies for PClk (controller logic), SynClk (RAC block), RefClk (DRCG

component), CTM (RDRAM component), and SCK (SIO block).

2.0 RAC Initialization

This step causes the INIT block to generate a sequence of pulses which resets the RAC, performs RAC

maintainance operations, and measures timing intervals in order to ensure clock stability.

3.0 RDRAM Initialization

This stage performs most of the steps needed to initialize the RDRAMs. The rest are performed in stages 5.0,

6.0, and 7.0. All of the steps in 3.0 are carried out through the SIO block interface.

3.1/3.2 SIO Reset

After a delay of tPAUSE from step 1.0, this reset operation is performed before any SIO control register read or

write transactions. It clears six registers (TEST34, CCA, CCB, SKIP, TEST78, and TEST79) and places the

INIT register into a special state (all bits cleared except SKP and SDEVID fields are set to ones).

3.3 Write TEST77 Register

The TEST77 register must be explicitly written with zeros before any other registers are read or written.

3.4 Write TCYCLE Register

The TCYCLE register is written with the cycle time tCYCLE of the CTM clock (for Channel and RDRAMs) in

units of 64ps. The tCYCLE value is determined in stage 1.0.

3.5 Write SDEVID Register

The SDEVID (serial device identification) register of the RDRAM is written with a unique address value so

that directed SIO read and write transactions can be performed. This address value increases from 0 to 31

according to the distance an RDRAM is from the ASIC component on the SIO bus (the closest RDRAM is

address 0).

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