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PD488588FF Datasheet(PDF) 44 Page - Elpida Memory |
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PD488588FF Datasheet(HTML) 44 Page - Elpida Memory |
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44 / 79 page  Data Sheet E0251N20 (Ver. 2.0) 44 µµµµPD488588FF-C80-40 Figure 22-1 Control Registers (5/7) Control Register : TPARM Address : 04816 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 TCDLY0 TCLS TCAL Read/write register. Reset value is undefined. Field Description TCDLY0 Specifies the tCDLY0-C core parameter in tCYCLE units. This adds a programmable delay to Q (read data) packets, permitting round trip read delay to all device to be equalized. This field may be written with the values “010” (2 •tCYCLE) through “101” (5 •tCYCLE). TCLS1..0 Specifies the tCLS-C core parameter in tCYCLE units. Should be “10” (2 •tCYCLE). TCAS1..0 Specifies the tCAS-C core parameter in tCYCLE units. This should be “10” (2 •tCYCLE). The equations relating the core parameters to the datasheet parameters follow: tCAS-C=2 •tCYCLE tCLS-C=2 •tCYCLE tCPS-C=1 •tCYCLE Not programmable tOFFP=tCPS-C + tCAS-C + tCLS-C - 1 •tCYCLE =4 •tCYCLE tRCD=tRCD-C + 1 •tCYCLE – tCLS-C =tRCD-C - 1 •tCYCLE tCAC=3 •tCYCLE + tCLS-C + tCDLY0-C + tCDLY1-C (see table below programming ranges) TCDLY0 tCDLY0-C TCDLY1 tCDLY1-C tCAC@tCYCLE=3.30 ns tCAC@tCYCLE=2.50 ns 010 2 •tCYCLE 000 0 •tCYCLE 7 •tCYCLE not allowed 011 3 •tCYCLE 000 0 •tCYCLE 8 •tCYCLE 8 •tCYCLE 011 3 •tCYCLE 001 1 •tCYCLE 9 •tCYCLE 9 •tCYCLE 011 3 •tCYCLE 010 2 •tCYCLE 10 •tCYCLE 10 •tCYCLE 100 4 •tCYCLE 010 2 •tCYCLE 11 •tCYCLE 11 •tCYCLE 101 5 •tCYCLE 010 2 •tCYCLE 12 •tCYCLE 12 •tCYCLE Control Register : TFRM Address : 04916 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 TFRM3..0 Read/write register. Reset value is undefined. Field Description TFRM3..0 Specifies the position of the framing point in tCYCLE units. This value must be greater than or equal to the tFRM,MIN parameter. This is the minimum offset between a ROW packet (which places a device at ATTN) and the first COL packet (directed to that device) which must be framed. This field may be written with the value “0111” (7 •tCYCLE) through “1010” (10 •tCYCLE). TFRM is usually set to the value which matches the largest tRCD,MIN parameter (modulo 4 •tCYCLE) that is present in an RDRAM in the memory system. Thus, if an RDRAM with tRCD,MIN=11•tCYCLE were present, then TFRM would be programmed to 7 •tCYCLE. |
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