VIN

4

5.2V

REGS

VDD

VDR

12

5

gm

BIAS

EN1

EN2

VBG

0.6V

CLOCK/

PLL

FREQ/

SYNC

CLKOUT

18

23

17

28

VSW1

+

-

20 éA

+

+

+

-

+

+

+

-

8.5 éA

SS2

TRK2

TRK1

SS1

RAMP1

RAMP2

ILIM1

ILIM2

PGND2

PGND1

VSW2

CURRENT

EMULATION

AND

SLOPE

COMPENSATION

REF1

REF2

9

32

8

7

1

2

+

-

SYSTEM_CLOCK

VSW1

VSW2

PWM LOGIC

DUTY CYCLE

AND

DRIVER

CONTROL

EN1

EN2

SYSTEM_REF

REF1

REF2

VOUT1, VOUT2

MONITOR

EN1

EN2

SYSTEM_REF

VCB1

HG1

LG1

VSW1

PGND1

COMP1

FB1

FB1

EA1_GND

EA2_GND

FB2

FB2

COMP2

PGOOD1

PGOOD2

VCB2

HG2

VDR

LG2

20

19

22

21

30

11

10

31

6

15

14

13

16

3

25

26

27

24

VSW2

VDR

++

+

+

SENSING

EN1

or FAULT

EN2

or

FAULT

20 éA

PGND2

OC1

OC2

SENSING

LG2

LG2

LG1

LG1

FAULT

8.5 éA

250Ö

250Ö

SGND

29

1 kÖ 1 kÖ

+

-

+

-

FB2

FB1

REF2

REF1

LM3000

www.ti.com

SNVS612A – JULY 2009 – REVISED JULY 2009

Block Diagram

Functional Description

THEORY OF OPERATION

The LM3000 is a dual emulated current-mode PWM synchronous controller. Unlike traditional peak current-mode

controllers which sense the current while the high-side FET is on, the LM3000 senses current while the low-side

FET is on. It then emulates the peak current waveform and uses that information to regulate the output voltage.

The blanking time when the high-side FET first turns on that is normally associated with high-side sensing is not

needed, allowing high-side ON pulses as low as 50 ns. The LM3000 therefore has both excellent line transient

response and the ability to regulate low output voltages from high input voltages.

Copyright © 2009, Texas Instruments Incorporated

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