LM3000 datasheet(12/41 Pages) TI1

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RT2

RT1

TRK2

FB2

LM3000

VOUT1

RFBT1

RFBB1

VOUT2

RFBT2

RFBB2

TRK1

FB1

VDD

tSS >

VOUT x COUT

ILIMIT ± IOUT

tSS =

CSS x 0.6V

8.5 é

LM3000

SNVS612A – JULY 2009 – REVISED JULY 2009

www.ti.com

STARTUP

After the EN1 or EN2 current exceeds the enable ON threshold and the voltage at the VDD pin reaches 2.2V, an

internal 8.5 µA current source charges the soft-start capacitor of the enabled channel. Once soft-start is complete

the converter enters steady state operation. Current limit is enabled during soft-start in case of a short circuit at

the output. The soft-start time is calculated as:

(1)

To avoid current limit during startup, the soft-start time tSS should be substantially longer than the time required

to charge COUT to VOUT at the maximum output current. To meet this requirement:

(2)

STARTUP INTO OUTPUT PRE-BIAS

If the output capacitor of the LM3000 has been charged up to some pre-bias level before the converter is

enabled, the chip will force the soft-start capacitor to the same voltage as the FB pin. This will cause the output

to ramp up from the existing output voltage without discharging it. During the soft-start ramp, the low-side FET is

disabled whenever the COMP voltage is below the active regulation voltage range.

LOW INPUT VOLTAGE

The LM3000 includes an internal 5.2V linear regulator connected from the VIN pin to the VDD pin. This linear

regulator feeds the logic and FET drive circuitry. For input voltages less than 5.5V, the VIN, VDD and VDR pins

can be tied together externally. This allows the full input voltage to be used for driving the power FETs and also

minimizes conduction loss in the LM3000.

TRACKING

The LM3000 has individual tracking inputs which control each output during soft-start. This allows the output

voltage slew rates to be controlled for loads that require precise sequencing. When the tracking function is not

being used the TRK1 or TRK2 pins should be connected directly to the VDD pin.

During start-up, the error amplifier will follow the lower of the SS or TRK voltages. For design margin, the soft-

start time tSS should be set to 75% of the minimum expected rise time of the controlling supply. In the event that

the LM3000 is enabled with a pre-biased master supply controlling track, the soft-start capacitor will control the

tracking output voltage rise time. Pulling TRK down after a normal startup will cause the output voltage to follow

the track signal.

Figure 2. Tracking with VOUT1 Controlling VOUT2

Figure 2 shows a tracking example with the highest output voltage at VOUT1 controlling VOUT2. Tracking may be

set so that VOUT1 and VOUT2 both rise together. For this case, the equation governing the values of the tracking

divider resistors RT1 and RT2 is:

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