AT86RF233 datasheet(25/225 Pages) ATMEL

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MCU Wireless AT86RF233 [PRELIMINARY DATASHEET]

Atmel-8351E-MCU_Wireless-AT86RF233_Datasheet_072014

Figure 6-12. Packet Structure – SRAM Write Access.

reserved[4:0]

MOSI

PHY_STATUS

MISO

byte 1 (command byte)

ADDRESS[7:0]

byte 2 (address)

DATA[7:0]

byte 3 (data byte)

DATA[7:0]

byte n-1 (data byte)

DATA[7:0]

byte n (data byte)

As long as /SEL = L, every subsequent byte read or byte write increments the address

counter of the Frame Buffer until the SRAM access is terminated by /SEL = H.

Figure 6-13 and Figure 6-14 illustrate an example SPI sequence of an

Atmel AT86RF233 SRAM access to read and write a data package of five byte length,

respectively.

Figure 6-13. Example SPI Sequence – SRAM Read Access of a 5-byte Data Package.

COMMAND

ADDRESS

PHY_STATUS

DATA 2

DATA 1

DATA 4

DATA 3

DATA 5

SCLK

MOSI

MISO

/SEL

Figure 6-14. Example SPI Sequence – SRAM Write Access of a 5-byte Data Package.

COMMAND

ADDRESS

DATA 1

DATA 2

DATA 3

DATA 4

PHY_STATUS

DATA 5

SCLK

MOSI

MISO

/SEL

Notes:

1. The SRAM access mode is not intended to be used as an alternative to the

Frame Buffer access modes (see Section 6.3.2).

2. Frame Buffer access violations are not indicated by a TRX_UR interrupt when

using the SRAM access mode, for further details refer to Section 9.3.3.

6.4 Radio Transceiver Status information

Each Atmel AT86RF233 SPI access can return radio transceiver status information which

is a first byte transmitted out of MISO output as the serial data is being shifted into MOSI

input. Radio transceiver status information (PHY_STATUS) can be configured using

PHY_RSSI or IRQ_STATUS register as shown in below.

6.4.1 Register Description

Note:

1. Throughout this datasheet, underlined values indicate reset settings.

The TRX_CTRL_1 register is a multi-purpose register to control various operating

modes and settings of the radio transceiver.

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