AT86RF233 datasheet(4/225 Pages) ATMEL

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MCU Wireless AT86RF233 [PRELIMINARY DATASHEET]

Atmel-8351E-MCU_Wireless-AT86RF233_Datasheet_072014

9.3 Frame Buffer.......................................................................................................................................................... 118

9.3.1 Data Management ............................................................................................................................................................. 118

9.3.2 User accessible Frame Content......................................................................................................................................... 119

9.3.3 Interrupt Handling .............................................................................................................................................................. 119

9.4 Voltage Regulators (AVREG, DVREG) ................................................................................................................. 121

9.4.1 Overview............................................................................................................................................................................ 121

9.4.2 Configuration ..................................................................................................................................................................... 122

9.4.3 Data Interpretation............................................................................................................................................................. 122

9.4.4 Register Description .......................................................................................................................................................... 122

9.5 Battery Monitor (BATMON).................................................................................................................................... 124

9.5.1 Overview............................................................................................................................................................................ 124

9.5.2 Configuration ..................................................................................................................................................................... 124

9.5.3 Data Interpretation............................................................................................................................................................. 124

9.5.4 Interrupt Handling .............................................................................................................................................................. 125

9.5.5 Register Description .......................................................................................................................................................... 125

9.6 Crystal Oscillator (XOSC) ...................................................................................................................................... 127

9.6.1 Overview............................................................................................................................................................................ 127

9.6.2 Integrated Oscillator Setup ................................................................................................................................................ 127

9.6.3 External Reference Frequency Setup................................................................................................................................ 128

9.6.4 Master Clock Signal Output (CLKM).................................................................................................................................. 128

9.6.5 Register Description .......................................................................................................................................................... 129

9.7 Frequency Synthesizer (PLL) ................................................................................................................................ 132

9.7.1 Overview............................................................................................................................................................................ 132

9.7.2 RF Channel Selection........................................................................................................................................................ 132

9.7.3 PLL Settling Time and Frequency Agility........................................................................................................................... 133

9.7.4 Calibration Loops............................................................................................................................................................... 133

9.7.5 Interrupt Handling .............................................................................................................................................................. 134

9.7.6 Register Description .......................................................................................................................................................... 134

9.8 Automatic Filter Tuning (FTN) ............................................................................................................................... 139

9.8.1 Overview............................................................................................................................................................................ 139

9.8.2 Register Description .......................................................................................................................................................... 139

10 Radio Transceiver Usage .......................................................................................................141

10.1 Frame Receive Procedure................................................................................................................................... 141

10.2 Frame Transmit Procedure.................................................................................................................................. 142

11 AT86RF233 Extended Feature Set.........................................................................................143

11.1 Security Module (AES) ........................................................................................................................................ 143

11.1.1 Overview.......................................................................................................................................................................... 143

11.1.2 Security Module Preparation ........................................................................................................................................... 143

11.1.3 Security Key Setup .......................................................................................................................................................... 144

11.1.4 Security Operation Modes ............................................................................................................................................... 144

11.1.5 Data Transfer – Fast SRAM Access................................................................................................................................ 147

11.1.6 Start of Security Operation and Status ............................................................................................................................ 147

11.1.7 SRAM Register Summary................................................................................................................................................ 148

11.1.8 Register Description ........................................................................................................................................................ 148

11.2 Random Number Generator ................................................................................................................................ 151

11.2.1 Overview.......................................................................................................................................................................... 151

11.2.2 Register Description ........................................................................................................................................................ 151

11.3 High Data Rate Modes ........................................................................................................................................ 152

11.3.1 Overview.......................................................................................................................................................................... 152

11.3.2 High Data Rate Packet Structure..................................................................................................................................... 153

11.3.3 High Data Rate Frame Buffer Access.............................................................................................................................. 154

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