AT86RF233 datasheet(34/225 Pages) ATMEL

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MCU Wireless AT86RF233 [PRELIMINARY DATASHEET]

Atmel-8351E-MCU_Wireless-AT86RF233_Datasheet_072014

By reading the register after an interrupt is signaled at pin 24 (IRQ) the source of the

issued interrupt can be identified. A read access to this register resets all interrupt bits,

and so clears the IRQ_STATUS register.

Notes:

1. If register bit IRQ_MASK_MODE (register 0x04, TRX_CTRL_1) is set, an

interrupt event can be read from IRQ_STATUS register even if the interrupt

itself is masked; refer to Figure 6-22. However in that case no timing information

for this interrupt is provided.

2. If register bit IRQ_MASK_MODE (register 0x04, TRX_CTRL_1) is set, it is

recommended to read the interrupt status register 0x0F (IRQ_STATUS) first to

clear the history.

The TRX_CTRL_1 register is a multi-purpose register to control various operating

modes and settings of the radio transceiver.

Figure 6-25. Register TRX_CTRL_1.

Bit

0x04

PA_EXT_EN

IRQ_2_EXT_EN

TX_AUTO_CRC_

RX_BL_CTRL

TRX_CTRL_1

Read/Write

R/W

Reset value

Bit

0x04

SPI_CMD_MODE

IRQ_MASK_MODE

IRQ_POLARITY

TRX_CTRL_1

Read/Write

R/W

Reset value

•

Bit 6 - IRQ_2_EXT_EN

The register bit IRQ_2_EXT_EN controls external signaling for time stamping via pin 10

(DIG2).

Table 6-13. IRQ_2_EXT_EN.

Value

Description

IRQ_2_EXT_EN

Time stamping over pin 10 (DIG2) is disabled

1(1)

Time stamping over pin 10 (DIG2) is enabled

Notes: 1.

The pin 10 (DIG2) is also active if the corresponding interrupt event IRQ_2

(RX_START) mask bit in register 0x0E (IRQ_MASK) is set to zero.

The pin remains at high level until the end of the frame receive or transmit

procedure.

The timing of a received frame can be determined by a separate pin 10 (DIG2). If

on pin 10 (DIG2), similar to interrupt IRQ_2 (RX_START).

For further details refer to Section 11.6.

AT86RF233 Datasheet(PDF) 34 Page - ATMEL Corporation

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