GMS87C1102 datasheet(54/89 Pages) HYNIX

54 / 89 page

GMS81C1102 / GMS81C1202

Jan. 2002 ver 2.0

If it needed more higher frequency of PWM, it should be

reduced resolution.

The bit POL of TM1 decides the polarity of duty cycle.

If the duty value is set same to the period value, the PWM

output is determined by the bit POL ( 1: High, 0: Low ).

And if the duty value is set to "00H", the PWM output is

determined by the bit POL ( 1: Low, 0: High ).

It can be changed duty value when the PWM output. How-

erver the changed duty value is output after the current pe-

riod is over. And it can be maintained the duty value at

present output when changed only period value shown as

Figure 16-12 . As it were, the absolute duty time is not

changed in varying frequency. But the changed period val-

ue must greater than the duty value

Note: At PWM output start command, one first pulse would

be output abnormally. Because if user writes regis-

ter values while timer is in operaiton, these register

could be set with certain values at first. To prevent

this operation, user must stop PWM timer clock and

then set the duty and the period register values.

Figure 16-10 PWM Mode

Resolution

Frequency

T1CK[1:0]

= 00(125nS)

T1CK[1:0]

= 01(250nS)

T1CK[1:0]

= 10(1uS)

10-bit

7.8KHz

3.9KHz

0.98KHZ

9-bit

15.6KHz

7.8KHz

1.95KHz

8-bit

31.2KHz

15.6KHz

3.90KHz

7-bit

62.5KHz

31.2KHz

7.81KHz

Table 16-2 PWM Frequency vs. Resolution at 8MHz

÷ 1

÷ 2

÷ 8

PWM0HR

ADDRESS : D5H

RESET VALUE : ----0000

PWM0HR3PWM0HR2PWM0HR1PWM0HR0

---

XXX

MUX

T1CN

T1CK[1:0]

T1 ( 8-bit )

T1ST

0 : Stop

1 : Start

CLEAR

COMPARATOR

T1PDR(8-bit)

PWM0HR[1:0]

T1PPR(8-bit)

PWM0HR[3:2]

T1PDR(8-bit)

POL

PWM0O

RB4/

PWM0

T0 clock source

fxin

TM1

ADDRESS : D2H

RESET VALUE : 00000000

POL

16BIT

PWME

CAP1

T1CK1

T1CK0

T1CN

T1ST

010

XXX

[RBFUNC.4]

Period High

Duty High

Slave

Master

Bit Manipulation Not Available

X : The value IS "0" or "1" corresponding your operation.

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