GMS87C1102 datasheet(62/89 Pages) HYNIX

62 / 89 page

GMS81C1102 / GMS81C1202

Jan. 2002 ver 2.0

Figure 19-3 Timing chart of Interrupt Acceptance and Interrupt Return Instruction

A interrupt request is not accepted until the I-flag is set to

"1" even if a requested interrupt has higher priority than

that of the current interrupt being serviced.

When nested interrupt service is required, the I-flag should

be set to "1" by “EI” instruction in the interrupt service

program. In this case, acceptable interrupt sources are se-

lectively enabled by the individual interrupt enable flags.

Saving/Restoring General-purpose Register

During interrupt acceptance processing, the program

counter and the program status word are automatically

saved on the stack, but accumulator and other registers are

not saved itself. These registers are saved by the software

if necessary. Also, when multiple interrupt services are

nested, it is necessary to avoid using the same data memory

area for saving registers.

The following method is used to save/restore the general-

purpose registers.

Example: Register save using push and pop instructions

General-purpose register save/restore using push and pop

instructions;

V.L.

System clock

Address Bus

SP-1

SP-2

V.H.

New PC

V.L.

Data Bus

Not used

PCH

PCL

PSW

ADL

OP code

ADH

Instruction Fetch

Internal Read

Internal Write

Interrupt Processing Step

Interrupt Service Task

V.L. and V.H. are vector addresses.

ADL and ADH are start addresses of interrupt service routine as vector contents.

Basic Interval Timer

012H

0E3H

0FFE6H

0FFE7H

0EH

2EH

0E312H

0E313H

Entry Address

Correspondence between vector table address for BIT interrupt

and the entry address of the interrupt service program.

Vector Table Address

INTxx:

PUSH

;SAVE ACC.

;SAVE X REG.

;SAVE Y REG.

interrupt processing

POP

RETI

;RESTORE Y REG.

;RESTORE X REG.

;RESTORE ACC.

;RETURN

main task

interrupt

service task

saving

registers

restoring

registers

acceptance of

interrupt

interrupt return

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