28F002BC datasheet(16/37 Pages) INTEL

16 / 37 page

28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY

PRELIMINARY

Read Status Register (70H)

This is one of three commands that is executable

while the WSM is operating. After this command is

written, a read of the device will output the contents

of the status register, regardless of the address

presented to the device. The device automatically

enters this mode after program or erase has

completed.

Clear Status Register (50H)

The WSM can set the Program Status and Erase

Status bits in the status register to “1,” but it cannot

clear them to “0.”

The status register is operated in this fashion for

two reasons, the first is synchronization. Since the

WSM does not know when the host CPU has read

the status register, it would not know when to clear

the status bits. Second, if the CPU is programming

a string of bytes, it may be more efficient to query

the status register after programming the string.

Thus, if any errors exist while programming the

string,

the

status

will

return

the

accumulated

error

status.

The

Clear

Status

VPP Status bits to “0.”

Program Setup (40H)

This command simply sets the CUI into a state

such that the next write will load the Address and

Data registers. After this command is executed, the

outputs

default

the

status

Two

consecutive Read Array commands (FFH) are

required to reset to Read Array after the Program

Setup command.

Program

The write following the Program Setup command

will latch address and data. Also, the CUI initiates

the WSM to begin execution of the program

algorithm. The device outputs status register data

when OE# is enabled. To read array data after the

program operation is completed, a Read Array

command is required.

Erase Setup (20H)

The Erase Setup command prepares the CUI for

the Erase Confirm command. No other action is

taken. If the next command is not an Erase Confirm

command, then the CUI will set both the Program

Status and Erase Status bits of the status register

to a “1,” place the device into read status register

mode, and wait for another command.

Erase Confirm (D0H)

If the previous command was an Erase Setup

command, then the CUI will enable the WSM to

erase, at the same time closing the address and

data latches, and respond only to the Read Status

WSM is executing, the device will output status

OE# or CE#. If the previous command was not the

Erase Setup command (20H), the Erase Confirm

command is ignored. Status Register bits 4 and 5

are both set to indicate an invalid command

sequence.

Erase Suspend (B0H)

This command is only valid while the WSM is

executing an erase operation. At all other times,

this command is ignored. After this command has

been executed, the CUI will set a signal that directs

the WSM to suspend erase operations. While

waiting for the erase to be suspended, the CUI

responds

only

the

Read

Status

command or to the Erase Resume command. Once

the WSM has reached the Suspend state, it will set

an output in the CUI that allows the CUI to respond

to the Read Array, Read Status Register, and Erase

Resume commands. In this mode, the CUI will not

respond to any other commands. The WSM will

also set the WSM and Erase Suspend status bits to

a “1.” The WSM will continue to run, idling in the

Suspend state, regardless of the state of all input

control pins except VPP and RP#. If VPP is taken

below VPPLK, the VPP low status bit (SR.3) will be

set and the WSM will abort the suspended erase

operation. If active, RP# will immediately shut down

the WSM and the remainder of the chip. During a

suspend operation, the data and address latches

will remain closed, but the address pads are able to

drive the address into the read path.

28F002BC Datasheet(PDF) 16 Page - Intel Corporation

28F002BC Datasheet(HTML) 16 Page - Intel Corporation

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