E

28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY

33

PRELIMINARY

28F002BC-80

28F002BC-120

Symbol

Parameter

Notes

100 pF

100 pF

Units

Min

Max

Min

Max

Write Cycle Time

80

120

ns

RP# High Recovery to CE# Going

Low

215

215

ns

WE# Setup to CE# Going Low

0

0

ns

Boot Block Lock Setup to CE# Going

High

6, 8

100

100

ns

5, 8

100

100

ns

Address Setup to CE# Going High

3

50

50

ns

Data Setup to CE# Going High

4

50

50

ns

CE# Pulse Width

50

50

ns

Data Hold Time from CE# High

4

0

0

ns

Address Hold Time from CE# High

3

0

0

ns

WE # Hold Time from CE# High

0

0

ns

CE# Pulse Width High

30

30

ns

Duration of Programming Operation

2, 5

6

6

µs

Duration of Erase Operation (Boot)

2, 5, 6

0.3

0.3

s

Duration of Erase Operation

(Parameter)

2, 5

0.3

0.3

s

Duration of Erase Operation (Main)

2, 5

0.6

0.6

s

5, 8

0

0

ns

6, 8

0

0

ns

Boot Block Lock Delay

7, 8

100

100

ns

NOTES:

See WE# Controlled Write Operations for notes 1 through 8.

9.

Chip-Enable controlled writes: write operations are driven by the valid combination of CE# and WE# in systems where

CE# defines the write pulse-width (within a longer WE# timing waveform), all set-up, hold and inactive WE# times should

be measured relative to the CE# waveform.