28F002BC datasheet(18/37 Pages) INTEL

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28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY

PRELIMINARY

Table 5. Status Register Bit Definition

WSMS

ESS

DWS

VPPS

6543

210

NOTES:

SR.7 = WRITE STATE MACHINE STATUS (WSMS)

1 = Ready

0 = Busy

The Write State Machine bit must first be checked to

determine program or Block Erase completion,

before the Program or Erase Status bits are checked

for success.

SR.6 = ERASE-SUSPEND STATUS (ESS)

1 = Erase Suspended

0 = Erase In Progress/Completed

When Erase Suspend is issued, the WSM halts

execution and sets both the WSMS and ESS bits to

“1.” The ESS bit remains set to “1” until an Erase

Resume command is issued.

SR.5 = ERASE STATUS

1 = Error In Block Erasure

0 = Successful Block Erase

When this bit is set to “1,” the WSM has applied the

maximum number of erase pulses to the block and is

still unable to successfully verify block erasure.

SR.4 = PROGRAM STATUS

1 = Error in Byte Program

0 = Successful Byte Program

When this bit is set to “1,” the WSM has attempted

but failed to program a byte.

SR.3 = VPP STATUS

1 = VPP Low Detect, Operation Abort

0 = VPP OK

The VPP Status bit, unlike an A/D converter, does not

provide continuous indication of VPP level, but it does

check the VPP level intermittently. The WSM

interrogates VPP level only after the program or

erase command sequences have been entered, and

informs the system if VPP has not been switched on.

If VPP ever goes below VPPLK (even during an Erase

Suspend), the status register will set this bit and

abort the operation in progress, even if VPP is

returned to a valid level. The VPP Status bit is not

guaranteed to report accurate feedback between

VPPLK and VPPH.

SR.2–SR.0 = RESERVED FOR FUTURE

ENHANCEMENTS

These bits are reserved for future use and should be

masked out when polling the status register.

3.3.4

ERASE MODE

Erase Setup and Erase Confirm commands to the

CUI, along with the address identifying the block to

be erased. This address is latched internally when

the Erase Confirm command is issued. Block

erasure results in all bits within the block being set

to “1.”

If the Erase Confirm command does not follow the

Erase

Setup

command,

the

status

responds by setting both SR.4 and SR.5 to “1” to

indicate an invalid command sequence. The WSM

returns to read status register mode.

The WSM then executes a sequence of internally

timed events to:

Program all bits within the block to “0.”

Verify

that

all

bits

within

the

block

are

sufficiently programmed to “0.”

Erase all bits within the block (set all bits to “1”).

Verify

that

all

bits

within

the

block

are

sufficiently erased.

While the erase sequence is executing, bit 7 of the

status register is a “0.”

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