D8088 datasheet(13/30 Pages) INTEL

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8088

231456 – 9

Figure 9 Interrupt Acknowledge Sequence

External Synchronization via TEST

As an alternative to interrupts the 8088 provides a

single software-testable input pin (TEST) This input

is utilized by executing a WAIT instruction The sin-

gle WAIT instruction is repeatedly executed until the

TEST input goes active (LOW) The execution of

WAIT does not consume bus cycles once the queue

is full

If a local bus request occurs during WAIT execution

the 8088 3-states all output drivers If interrupts are

enabled the 8088 will recognize interrupts and pro-

cess them The WAIT instruction is then refetched

and reexecuted

Basic System Timing

In minimum mode the MNMX pin is strapped to

VCC and the processor emits bus control signals

compatible with the 8085 bus structure In maximum

mode the MNMX pin is strapped to GND and the

processor emits coded status information which the

8288 bus controller uses to generate MULTIBUS

compatible bus control signals

System TimingMinimum System

(See Figure 8)

The read cycle begins in T1 with the assertion of the

address latch enable (ALE) signal The trailing (low

going) edge of this signal is used to latch the ad-

dress information which is valid on the address

data

bus

(AD0 – AD7)

this

time

into

the

82828283 latch Address lines A8 through A15 do

not need to be latched because they remain valid

throughout the bus cycle From T1 to T4 the IOM

signal indicates a memory or IO operation At T2

the address is removed from the addressdata bus

and the bus goes to a high impedance state The

read control signal is also asserted at T2 The read

(RD) signal causes the addressed device to enable

its data bus drivers to the local bus Some time later

valid data will be available on the bus and the ad-

dressed device will drive the READY line HIGH

When the processor returns the read signal to a

HIGH level the addressed device will again 3-state

its bus drivers If a transceiver is required to buffer

the 8088 local bus signals DTR and DEN are pro-

vided by the 8088

A write cycle also begins with the assertion of ALE

and the emission of the address The IOM signal is

again asserted to indicate a memory or IO write

operation In T2 immediately following the address

emission the processor emits the data to be written

into the addressed location This data remains valid

until at least the middle of T4 During T2 T3 and

Tw the processor asserts the write control signal

The write (WR) signal becomes active at the begin-

ning of T2 as opposed to the read which is delayed

somewhat into T2 to provide time for the bus to

float

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