8088

Table 1 Pin Description

(Continued)

Symbol Pin No

Type

Name and Function

HOLD

HLDA

31 30

I O

HOLD

indicates that another master is requesting a local bus ‘‘hold’’ To be

acknowledged HOLD must be active HIGH The processor receiving the ‘‘hold’’

request will issue HLDA (HIGH) as an acknowledgement in the middle of a T4 or

Ti clock cycle Simultaneous with the issuance of HLDA the processor will float

the local bus and control lines After HOLD is detected as being LOW the

processor lowers HLDA and when the processor needs to run another cycle it

will again drive the local bus and control lines HOLD and HLDA have internal

pull-up resistors

Hold is not an asynchronous input External synchronization should be provided if

the system cannot otherwise guarantee the set up time

SSO

34

O

STATUS LINE

is logically equivalent to SO in the maximum mode The

combination of SSO IOM and DTR allows the system to completely decode the

current bus cycle status

IOM

DTR

SSO

Characteristics

1(HIGH)

0

0

Interrupt Acknowledge

1

0

1

Read IO Port

1

1

0

Write IO Port

1

1

1

Halt

0(LOW)

0

0

Code Access

0

0

1

Read Memory

0

1

0

Write Memory

0

1

1

Passive

GND) Only the pin functions which are unique to maximum mode are described all other pin functions are as

described above

Symbol

Pin No

Type

Name and Function

S2 S1 S0 26–28

O

STATUS

is active during clock high of T4 T1 and T2 and is returned to the

passive state (111) during T3 or during Tw when READY is HIGH This status is

used by the 8288 bus controller to generate all memory and IO access control

signals Any change by S2 S1 orS0 during T4 is used to indicate the beginning

of a bus cycle and the return to the passive state in T3 and Tw is used to

indicate the end of a bus cycle

These signals float to 3-state OFF during ‘‘hold acknowledge’’ During the first

clock cycle after RESET becomes active these signals are active HIGH After

this first clock they float to 3-state OFF

S2

S1

S0

Characteristics

0(LOW)

0

0

Interrupt Acknowledge

0

0

1

Read IO Port

0

1

0

Write IO Port

0

1

1

Halt

1(HIGH)

0

0

Code Access

1

0

1

Read Memory

1

1

0

Write Memory

1

1

1

Passive

4