D8088 datasheet(5/30 Pages) INTEL

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8088

Table 1 Pin Description

(Continued)

Symbol

Pin No

Type

Name and Function

RQ GT0

RQ GT1

30 31

REQUESTGRANT

pins are used by other local bus masters to force the

processor to release the local bus at the end of the processor’s current bus

cycle Each pin is bidirectional with RQ GT0 having higher priority than RQ

GT1 RQ GT has an internal pull-up resistor so may be left unconnected

The requestgrant sequence is as follows (See Figure 8)

1 A pulse of one CLK wide from another local bus master indicates a local

bus request (‘‘hold’’) to the 8088 (pulse 1)

2 During a T4 or TI clock cycle a pulse one clock wide from the 8088 to the

requesting master (pulse 2) indicates that the 8088 has allowed the local

bus to float and that it will enter the ‘‘hold acknowledge’’ state at the next

CLK The CPU’s bus interface unit is disconnected logically from the local

bus during ‘‘hold acknowledge’’ The same rules as for HOLDHOLDA apply

as for when the bus is released

3 A pulse one CLK wide from the requesting master indicates to the 8088

(pulse 3) that the ‘‘hold’’ request is about to end and that the 8088 can

reclaim the local bus at the next CLK The CPU then enters T4

Each master-master exchange of the local bus is a sequence of three

pulses There must be one idle CLK cycle after each bus exchange Pulses

are active LOW

If the request is made while the CPU is performing a memory cycle it will

release the local bus during T4 of the cycle when all the following conditions

are met

1 Request occurs on or before T2

2 Current cycle is not the low bit of a word

3 Current cycle is not the first acknowledge of an interrupt acknowledge

sequence

4 A locked instruction is not currently executing

If the local bus is idle when the request is made the two possible events will

1 Local bus will be released during the next clock

2 A memory cycle will start within 3 clocks Now the four rules for a currently

active memory cycle apply with condition number 1 already satisfied

LOCK

indicates that other system bus masters are not to gain control of the

system bus while LOCK is active (LOW) The LOCK signal is activated by

the ‘‘LOCK’’ prefix instruction and remains active until the completion of the

next instruction This signal is active LOW and floats to 3-state off in ‘‘hold

acknowledge’’

QS1 QS0

24 25

QUEUE STATUS

provide status to allow external tracking of the internal

8088 instruction queue

The queue status is valid during the CLK cycle after which the queue

operation is performed

QS1

QS0

Characteristics

0(LOW)

No Operation

First Byte of Opcode from Queue

1(HIGH)

Empty the Queue

Subsequent Byte from Queue

Pin 34 is always high in the maximum mode

D8088 Datasheet(PDF) 5 Page - Intel Corporation

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