8088

Table 1 Pin Description

(Continued)

Symbol

Pin No

Type

Name and Function

NMI

17

I

NON-MASKABLE INTERRUPT

is an edge triggered input which causes a

type 2 interrupt A subroutine is vectored to via an interrupt vector lookup

table located in system memory NMI is not maskable internally by

software A transition from a LOW to HIGH initiates the interrupt at the end

of the current instruction This input is internally synchronized

RESET

21

I

RESET

causes the processor to immediately terminate its present activity

The signal must be active HIGH for at least four clock cycles It restarts

execution as described in the instruction set description when RESET

returns LOW RESET is internally synchronized

CLK

19

I

CLOCK

provides the basic timing for the processor and bus controller It is

asymmetric with a 33% duty cycle to provide optimized internal timing

40

GND

1 20

GND

are the ground pins

MNMX

33

I

MINIMUMMAXIMUM

indicates what mode the processor is to operate in

The two modes are discussed in the following sections

functions which are unique to minimum mode are described all other pin functions are as described above

Symbol Pin No

Type

Name and Function

IOM

28

O

STATUS LINE

is an inverted maximum mode S2 It is used to distinguish a

memory access from an IO access IOM becomes valid in the T4 preceding a

bus cycle and remains valid until the final T4 of the cycle (IO e HIGH M e

LOW) IOM floats to 3-state OFF in local bus ‘‘hold acknowledge’’

WR

29

O

WRITE

strobe indicates that the processor is performing a write memory or write

IO cycle depending on the state of the IOM signal WR is active for T2 T3 and

Tw of any write cycle It is active LOW and floats to 3-state OFF in local bus

‘‘hold acknowledge’’

INTA

24

O

INTA

is used as a read strobe for interrupt acknowledge cycles It is active LOW

during T2 T3 and Tw of each interrupt acknowledge cycle

ALE

25

O

ADDRESS LATCH ENABLE

is provided by the processor to latch the address

into an address latch It is a HIGH pulse active during clock low of T1 of any bus

cycle Note that ALE is never floated

DTR

27

O

DATA TRANSMITRECEIVE

is needed in a minimum system that desires to use

a data bus transceiver It is used to control the direction of data flow through the

transceiver Logically DTR is equivalent to S1 in the maximum mode and its

timing is the same as for IOM (T e HIGH R e LOW) This signal floats to

3-state OFF in local ‘‘hold acknowledge’’

DEN

26

O

DATA ENABLE

is provided as an output enable for the data bus transceiver in a

minimum system which uses the transceiver DEN is active LOW during each

memory and IO access and for INTA cycles For a read or INTA cycle it is

active from the middle of T2 until the middle of T4 while for a write cycle it is

active from the beginning of T2 until the middle of T4 DEN floats to 3-state OFF

during local bus ‘‘hold acknowledge’’

3