D8088 datasheet(6/30 Pages) INTEL

6 / 30 page

8088

231456 – 3

Figure 3 Memory Organization

FUNCTIONAL DESCRIPTION

Memory Organization

The processor provides a 20-bit address to memory

which locates the byte being referenced The memo-

ry is organized as a linear array of up to 1 million

bytes addressed as 00000(H) to FFFFF(H) The

memory is logically divided into code data extra

data and stack segments of up to 64K bytes each

with each segment falling on 16-byte boundaries

(See Figure 3)

All memory references are made relative to base ad-

dresses contained in high speed segment registers

The segment types were chosen based on the ad-

dressing needs of programs The segment register

to be selected is automatically chosen according to

the rules of the following table All information in one

segment type share the same logical attributes (eg

code or data) By structuring memory into relocat-

able areas of similar characteristics and by automati-

cally selecting segment registers

programs are

shorter faster and more structured

Word (16-bit) operands can be located on even or

odd address boundaries For address and data oper-

ands the least significant byte of the word is stored

in the lower valued address location and the most

significant byte in the next higher address location

The BIU will automatically execute two fetch or write

cycles for 16-bit operands

Memory

Segment

Segment Selection Rule

Reference Used

Instructions

CODE (CS)

Automatic with all instruction prefetch

Stack

STACK (SS)

All stack pushes and pops Memory references

relative to BP base register except data references

Local Data

DATA (DS)

Data references when relative to stack destination

of string operation or explicity overridden

External (Global) Data

EXTRA (ES)

Destination of string operations Explicitly selected

using a segment override

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