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D8088 Datasheet(PDF) 22 Page - Intel Corporation |
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D8088 Datasheet(HTML) 22 Page - Intel Corporation |
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22 / 30 page ![]() 8088 AC CHARACTERISTICS (Continued) TIMING RESPONSES Symbol Parameter 8088 8088-2 Units Test Min Max Min Max Conditions TCLML Command Active Delay 10 35 10 35 ns (Note 1) TCLMH Command Inactive Delay 10 35 10 35 ns (Note 1) TRYHSH READY Active to 110 65 ns Status Passive (Note 3) TCHSV Status Active Delay 10 110 10 60 ns TCLSH Status Inactive Delay 10 130 10 70 ns TCLAV Address Valid Delay 10 110 10 60 ns TCLAX Address Hold Time 10 10 ns TCLAZ Address Float Delay TCLAX 80 TCLAX 50 ns TSVLH Status Valid to ALE High 15 15 ns (Note 1) TSVMCH Status Valid to MCE High 15 15 ns (Note 1) TCLLH CLK Low to ALE Valid 15 15 ns (Note 1) TCLMCH CLK Low to MCE (Note 1) 15 15 ns TCHLL ALE Inactive Delay (Note 1) 15 15 ns TCLMCL MCE Inactive Delay (Note 1) 15 15 ns TCLDV Data Valid Delay 10 110 10 60 ns TCHDX Data Hold Time 10 10 ns CL e 20–100 pF for TCVNV Control Active Delay 5 45 5 45 ns All 8088 Outputs (Note 1) in Addition to TCVNX Control Inactive Delay 10 45 10 45 ns Internal Loads (Note 1) TAZRL Address Float to 0 0 ns Read Active TCLRL RD Active Delay 10 165 10 100 ns TCLRH RD Inactive Delay 10 150 10 80 ns TRHAV RD Inactive to Next TCLCLb45 TCLCLb40 ns Address Active TCHDTL Direction Control 50 50 ns Active Delay (Note 1) TCHDTH Direction Control 30 30 ns Inactive Delay (Note 1) TCLGL GT Active Delay 85 50 ns TCLGH GT Inactive Delay 85 50 ns TRLRH RD Width 2TCLCLb75 2TCLCLb50 ns TOLOH Output Rise Time 20 20 ns From 08V to 20V TOHOL Output Fall Time 12 12 ns From 20V to 08V NOTES 1 Signal at 8284 or 8288 shown for reference only 2 Setup requirement for asynchronous signal only to guarantee recognition at next CLK 3 Applies only to T3 and wait states 4 Applies only to T2 state (8 ns into T3 state) 22 |
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