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80960SB Datasheet(PDF) 8 Page - Intel Corporation

Part # 80960SB
Description  EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS
PDF  38 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

80960SB Datasheet(HTML) 8 Page - Intel Corporation

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80960SB
Figure 3. Instruction Formats
Control
Compare and
Branch
Register to
Register
Memory Access---
Short
Memory Access---
Long
Opcode
Displacement
Opcode
Displacement
Reg/Lit
Reg
M
Displacement
Opcode
Opcode
Opcode
Reg
Reg
Reg
Reg/Lit
Base
Base
M
Modes
Mode
Ext’d Op
Reg/Lit
X
Offset
Scale
xx
Offset
1.1.1
Memory Space And Addressing Modes
The
80960SB
offers
a
linear
programming
environment so that all programs running on the
processor are contained in a single address space.
Maximum address space size is 4 Gigabytes (232
bytes).
For ease of use the 80960SB has a small number of
addressing modes, but includes all those necessary
to ensure efficient execution of high-level languages
such as C. Table 2 lists the memory addressing
modes.
Table 2. Memory Addressing Modes
•
12-Bit Offset
•
32-Bit Offset
•
Register-Indirect
•
Register + 12-Bit Offset
•
Register + 32-Bit Offset
•
Register + (Index-Register x Scale-Factor)
•
Register x Scale Factor + 32-Bit Displacement
•
Register + (Index-Register x Scale-Factor) +
32-Bit Displacement
Scale-Factor is 1, 2, 4, 8 or 16
1.1.2
Data Types
The 80960SB recognizes the following data types:
Numeric:
•
8-, 16-, 32- and 64-bit ordinals
•
8-, 16-, 32- and 64-bit integers
•
32-, 64- and 80-bit real numbers
Non-Numeric:
•
Bit
•
Bit Field
•
Triple Word (96 bits)
•
Quad-Word (128 bits)
1.1.3
Large Register Set
The 80960SB programming environment includes a
large number of registers. In fact, 32 registers are
available at any time. The availability of this many
registers greatly reduces the number of memory
accesses required to perform algorithms, which
leads to greater instruction processing speed.
There are two types of general-purpose register:
local and global. The global registers consist of
sixteen 32-bit registers (g0 though g15) and four



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