Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent

licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.

© INTEL CORPORATION, 1993

November 1993

Order Number: 272207-002

80960SB

EMBEDDED 32-BIT MICROPROCESSOR

WITH 16-BIT BURST DATA BUS

The 80960SB is a member of Intel’s i960

embedded applications. It includes a 512-byte instruction cache, an integrated floating-point unit and a built-in

interrupt controller. The 80960SB has a large register set, multiple parallel execution units and a 16-bit burst

bus. Using advanced RISC technology, this high performance processor is capable of execution rates in excess

of 5 million instructions per second

applications including non-impact printers, network adapters and I/O controllers.

Figure 1. The 80960SB Processor’s Highly Parallel Architecture

* Relative to Digital Equipment Corporation’s VAX-11/780 at 1 MIPS (VAX-11™ is a trademark of Digital Equipment

Corporation)

— 16 MIPS* Burst Execution at 16 MHz

— 5 MIPS Sustained Execution at 16 MHz

— Direct Mapped

— Parallel Load/Decode for Uncached

Instructions

— Sixteen Global 32-Bit Registers

— Sixteen Local 32-Bit Registers

— Four Local Register Sets Stored

On-Chip

— Register Scoreboarding

— 4 Direct Interrupt Pins

— 31 Priority Levels, 256 Vectors

— Fully IEEE 754 Compatible

— 25.6 Mbytes/s Burst

— Up to 16 Bytes Transferred per Burst

— 84-Lead Plastic Leaded Chip Carrier

(PLCC)

80960KA/KB/CA/CF Processors

INSTRUCTION

FETCH UNIT

512-BYTE

INSTRUCTION

CACHE

INSTRUCTION

DECODER

MICRO-

INSTRUCTION

SEQUENCER

MICRO-

INSTRUCTION

ROM

32-BIT

BUS

CONTROL

LOGIC

32-BIT

INSTRUCTION

EXECUTION

UNIT

64- BY 32-BIT

LOCAL

REGISTER

CACHE

SIXTEEN

32-BIT GLOBAL

REGISTERS

32-BIT

ADDRESS

16-BIT

BURST

BUS

FOUR

80-BIT FP

REGISTERS

80-BIT

FPU