82091AA datasheet(49/204 Pages) INTEL

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82091AA

Bit

Description

RESERVED

SERIAL PORT B TEST MODE (SBTEST)

The serial port test mode provides user access to the

output of the baud out generator When SBTESTe1 (and the DLAB bit is 1 in the LCR) the Serial

Port B test mode is enabled and the baud rate clock is output on the SOUTB pin (Figure 15) When

SBTESTe0 the Serial Port B test mode is disabled

SERIAL PORT B AUTO POWERDOWN ENABLE (SBAPDN)

This bit enablesdisables auto

powerdown When SBAPDNe1 Serial Port B can enter auto powerdown if the required conditions

are met The required conditions are that the transmit and receive FIFOs are empty and the timeout

counter has expired When SBAPDNe0 auto powerdown is disabled

SERIAL PORT B RESET (SBRESET)

When SBRESETe1 Serial Port B is reset (ie all

programming and current state information is lost) This is the same state the module would be in

after a hard reset (RSTDRV asserted) When resetting the serial port via this configuration bit the

software must toggle this bit and ensure the reset active time (SBRESETe1) of 113 ms minimum is

met

SERIAL PORT B IDLE STATUS (SBIDLE)

When Serial Port B is in an idle state the 82091AA sets

this bit to 1 Serial Port B is in the idle state when the transmit and receive FIFOs are empty and the

timeout counter has expired Note that these are the same conditions that apply to entering auto

powerdown When serial port B is not in an idle state the 82091AA sets this bit to 0 Direct

powerdown does not affect this bit and in auto powerdown this bit is only set toa1ifthe receive

and transmit FIFOs are empty This bit is read only

During a hard reset (RSTDRV asserted) the 82091AA sets this bit to 0 However because the serial

port is typically initialized by software before the idle conditions are met the defaullt state is shown

as undefined

SERIAL PORT B DIRECT POWERDOWN (SBDPDN)

When SBDPDNe1 Serial Port B is placed in

powerdown mode Setting this bit to 0 brings the module out of direct powerdown mode Setting bit 2

(SBRESET) of this register to 1 will also bring Serial Port B out of the direct powerdown mode

NOTE

Direct powerdown resets the receiver and transmitter portions of the serial port including the

receive and transmit FIFOs To ensure that the resetting of the FIFOs does not cause data

loss the SBIDLE bit should be 1 before placing the serial port into direct powerdown

41131 Serial Port AB Configuration

The bits which enable the serial ports (bit 0 in both

the SACFG1 and SBCFG1 registers) and the bits

which provide for serial port direct powerdown (bit 0

in both the SACFG2 and SBCFG2 registers) are not

mutually exclusive The partial circuit and truth table

for the two bits shows that it is possible to enable

serial port A using SACFG1 for example yet still

read the serial port A SACFG2 direct powerdown bit

as a ‘‘1’’

When the SxCFG1 register bit 0 (serial port x en-

able) is written as a ‘‘1’’ (enable) the SxCFG2 regis-

ter bit 0 (serial port x powerdown) does not change

from a ‘‘1’’ (powerdown enable) to a ‘‘0’’ (power-

down disable) As can be seen in the circuit diagram

the READ activity does not see the register directly

Instead a MUXed output is seen by the READ activi-

ty The truth table for the two bits shows it is possi-

ble to enable a serial port yet still read the power-

down bit for that same port as a ‘‘1’’ or enabled

Truth Table for Reading the

EnablePowerdown Bit Status

Write Activity

Read Activity

SxCFG1

SxCFG2

SxCFG1

SxCFG2

Enable

Powerdown

Enable

Powerdown

0001

1010

1111

0101

82091AA Datasheet(PDF) 49 Page - Intel Corporation

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