82091AA datasheet(5/204 Pages) INTEL

5 / 204 page

CONTENTS

PAGE

6231 FIFO Operations

6232 DMA Transfers

6233 Reset FIFO and DMA Terminal Count Interrupt

6234 Programmed IO Transfers

6235 Data Compression

624 PARALLEL PORT EXTERNAL BUFFER CONTROL

625 PARALLEL PORT SUMMARY

70 SERIAL PORT

71 Register Description

711 THR(AB)TRANSMITTER HOLDING REGISTER

712 RBR(AB)RECEIVER BUFFER REGISTER

713 DLL(AB) DLM(AB)DIVISOR LATCHES (LSB AND MSB) REGISTERS

714 IER(AB)INTERRUPT ENABLE REGISTER

101

715 IIR(AB)INTERRUPT IDENTIFICATION REGISTER

102

716 FCR(AB)FIFO CONTROL REGISTER

104

717 LCR(AB)LINE CONTROL REGISTER

106

718 MCR(AB)MODEM CONTROL REGISTER

108

719 LSR(AB)LINE STATUS REGISTER

109

7110 MSR(AB)MODEM STATUS REGISTER

112

7111 SCR(AB)SCRATCHPAD REGISTER

113

72 FIFO Operations

114

721 FIFO INTERRUPT MODE OPERATION

114

722 FIFO POLLED MODE OPERATION

114

80 FLOPPY DISK CONTROLLER

115

81 Floppy Disk Controller Registers

115

811 SRBSTATUS REGISTER B (EREG ENe1)

117

812 DORDIGITAL OUTPUT REGISTER

118

813 TDRENHANCED TAPE DRIVE REGISTER

119

814 MSRMAIN STATUS REGISTER

121

815 DSRDATA RATE SELECT REGISTER

122

816 FDCFIFOFDC FIFO (DATA)

125

817 DIRDIGITAL INPUT REGISTER

126

818 CCRCONFIGURATION CONTROL REGISTER

127

82 Reset

128

821 HARD RESET AND CONFIGURATION REGISTER RESET

128

822 DOR RESET vs DSR RESET

128

83 DMA Transfers

128

84 Controller Phases

128

841 COMMAND PHASE

128

842 EXECUTION PHASE

129

82091AA Datasheet(PDF) 5 Page - Intel Corporation

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