82374EB datasheet(192/208 Pages) INTEL

192 / 208 page

82374EB82374SB

1352 STPCLK

TIED TO BOTH SOCKETS

To support a glueless upgrade socket it is necessary to tie STPCLK

to both sockets For P54CCT proces-

sor configuration the P54CT processor will disable P54C and the toggling of STPCLK

has no effect to P54C

For a P54CCM DP configuration the toggling of STPCLK

effects both processors (unless the processor is

in Autohalt state) Both processors respond with a STPGNT special bus cycle after recognizing STPCLK

low

Both of the STPGNT special bus cycles are passed onto PCI by the PCMC as PCI STPGNT special cycles

The PCI STPGNT PCI cycle causes the PCEB component to assert the STPGNT

signal depending on how

the SCE bit in PCEB is programmed The ESC recognizes the first STPGNT

assertion and negates

STPCLK

upon the Stop Clock timer expiration or a stop break event

1353 SMI

INTR (APIC MODE)

When the APIC is used for interrupt delivery additional considerations exist regarding ordering If local inter-

rupts (LINT01) are used in APIC mode then the system can not guarantee an ordering between the local

interrupts and any related SMI

events

In DP mode interrupts can generally be directed to a specific processor which may not be the same proces-

sor that the SMI

is directed The IRQ blocking logic in the ESC still operates with APIC delivery mode Thus

if an IRQ is enabled to cause an SMI

event it will be blocked until the CSMIGATE is cleared regardless of

where the IRQ or SMI is to be directed by the APIC

140 ELECTRICAL CHARACTERISTICS

141 Maximum Ratings

Case Temperature Under Bias

65 Cto110 C

Storage Temperature

65 Cto150 C

Supply Voltages with Respect to Ground

05V to VCC a 05V

Voltage On Any Pin

05V to VCC a 05V

Power Dissipation

070W fully loaded

055W with four slots

WARNING

Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage These

are stress ratings only Operating beyond the ‘‘Operating Conditions’’ is not recommended and ex-

tended exposure beyond ‘‘Operating Conditions’’ may affect reliability

142 NAND Tree

A NAND Tree is provided primarily for VILVIH testing The NAND Tree is also useful for Automated Test

Equipment (ATE) at board-level testing The NAND Tree allows the tester to test the solder connections for

each individual signal pin

The TEST pin along with IRQ5 and IRQ3 activates the NAND Tree Asserting TEST causes the output pulse

train to appear on the EISAHOLD pin IRQ5 must be driven high in order to enable the NAND Tree The

assertion of IRQ3 causes the ESC to disable its buffers

192

82374EB Datasheet(PDF) 192 Page - Intel Corporation

82374EB Datasheet(HTML) 192 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL