82374EB datasheet(189/208 Pages) INTEL

189 / 208 page

82374EB82374SB

290476 – E1

Figure 34 System Events and the Fast Off Timer

EXTSMI

The EXTSMI

input pin provides the system designer the capability to invoke SMM with external hardware

For example the EXTSMI

input could be connected to a ‘‘green button’’ permitting the user to enter the Fast

Off state by depressing a button The EXTSMI

generation of an SMI is enableddisabled in the SMIEN

Software Events

Software events (accessing the APMx Registers) indicate that the OS is passing power management informa-

tion to the SMI handler There are two Advanced Power Management (APM) registersAPM Control (APMC)

and APM Status (APMS) Registers These registers permit software to generate an SMI by writing to the

APMC Register For example the APMC can be used to pass an APM command between APM OS and BIOS

and the APMS Register could be used to pass data between the OS and the SMI handler For detailed

descriptions of these registers see Section 30 Register Description

The two APM Registers are located in normal IO space The PCEB subtractively decodes PCI accesses to

these registers and forwards the accesses to the EISA Bus The APM Registers are not accessible by EISA

masters Note that the remaining power management registers are located in PCI configuration space

133 SMI

And INIT Interaction

The SMI

input to the CPU is an edge sensitive signal When an S-series processor is reset (INIT asserted)

the processor resets the SMI

edge detect logic After INIT is negated it takes two clocks before the edge

detect circuit can catch an edge The ESC only asserts SMI

when INIT is negated If the ESC asserts SMI

and then the INIT signal is sampled asserted the ESC negates SMI

1331 CLOCK CONTROL

The CPU can be put in a low power state by asserting the STPCLK

signal STPCLK

is an interrupt to the

CPU However for this type of interrupt the CPU does not generate an interrupt acknowledge cycle Once the

STPCLK

interrupt is executed the CPU enters the stop grant state In this state the CPU’s internal clocks

are disabled and instruction execution is stopped The stop grant state is exited when the STPCLK

signal is

negated

189

82374EB Datasheet(PDF) 189 Page - Intel Corporation