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82374EB Datasheet(PDF) 185 Page - Intel Corporation |
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82374EB Datasheet(HTML) 185 Page - Intel Corporation |
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185 / 208 page ![]() 82374EB82374SB Table 38 Encoded Chip Select Decode ESC2 ESC1 ESC0 PERIPHERAL CS 0 0 0 COMACS 0 0 1 COMBCS 0 1 0 LPTCS 0 1 1 IDECS0 1 0 0 IDECS1 1 0 1 GPCS0 1 1 0 GPCS1 1 1 1 idle state NOTE Refer to Section 45 for the address decode of the peripheral chip selects 129 X-Bus Control And General Purpose Decode The X-Bus is a secondary data bus buffered from the EISA Bus The X-Bus is used to interface with peripheral devices that do not require a high speed interface Typically a discrete buffer device like a F245 is used to buffer the EISA Bus from the X-Bus The ESC provides two control signals XBUSTR and XBUSOE for the discrete F245 buffer NOTE The ESC directly supports X-Bus floppy disk controller and X-Bus IDE hard disk controller If IDE resides elsewhere (eg ISA Bus or PCI Bus) additional hardware is required to support the X-Bus floppy The additional hardware is used to modify the X-Bus control signals Figure 31 shows the logic needed to support an X-Bus floppy disk with IDE on the ISA or PCI bus 290476 – D9 Figure 31 185 |
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