82374EB datasheet(182/208 Pages) INTEL

182 / 208 page

82374EB82374SB

When the ESC detects an IO write to the internal port 00F0h the ESC deasserts the internal IRQ13 line to

the integrated Interrupt Controller At the same time the ESC asserts the IGNNE

signal The ESC keeps the

IGNNE

signal asserted until the FERR

signal is negated by the CPU

If the coprocessor error support is enabled in the EISA Clock Divider configuration register then the ESC

IRQ13 pins cannot be used and this pin should be tied to ground

290476 – 89

Figure 29 Coprocessor Interface Waveform

123 BIOS Interface

The ESC supports a total of 512 KBytes of BIOS memory The ESC asserts the LBIOSCS

signal for EISA or

ISA memory cycles decoded to be in the BIOS space The 512 KBytes of BIOS includes the conventional 128

KBytes of BIOS and 384 KBytes of enlarged BIOS The 128 KBytes of conventional BIOS is divided into

multiple regions Each region can be independently enabled or disabled by setting the appropriate bits in the

BIOS Chip Select A register and BIOS Chip Select B register The 128 KBytes of conventional BIOS is also

aliased at different locations within the memory space Refer to Section 41 BIOS Memory Space for details

The ESC generates the LBIOSCS

signal by internally latching the output of the BIOS address decode with

BALE signal The ESC asserts the LBIOSCS

for all read cycles in the enabled BIOS memory space The

ESC will assert LBIOSCS

signal for write cycles in the enabled BIOS memory space only if the BIOS Chip

Select B register bit 3 is set to 1 (BIOS write enable)

124 Keyboard Controller Interface

The ESC provides a complete interface to a glueless interface to a 8x42 Keyboard Controller The ESC

Keyboard Controller interface consists of Keyboard Controller Chip Select (KYBDCS ) signal Mouse interrupt

(ABFULL) signal The ESC also supports the fast Keyboard commands for CPU reset (ALTRST ) and ad-

dress A20 enable (ALTA20) by integrating Port 92h

182

82374EB Datasheet(PDF) 182 Page - Intel Corporation