82374EB datasheet(178/208 Pages) INTEL

178 / 208 page

82374EB82374SB

112 System Buffer Coherency ControlAPIC

During an interrupt sequence the system buffers must be flushed before the ESC’s IO APIC can send an

interrupt message to the local APIC (CPU’s APIC) The ESC and PCEB maintain buffer coherency when the

ESC receives an interrupt request for its IO APIC using the AFLUSH

signal

113 Power Management

In response to the ESC’s STPCLK

assertion the CPU sends out a stop grant bus cycle to indicate that it has

entered the stop grant state The PCEB informs the ESC of the stop grant cycle using the STPGNT

signal

114 EISA Data Swap Buffer Control Signals

The cycles in the EISA environment may require data size translations before the data can be transferred to its

intermediate or final destination As an example a 32-bit EISA master write cycle to a 16-bit EISA slave

requires a disassembly of a 32-bit Dword into 16 bit Words Similarly a 32-bit EISA master read cycle to a

16-bit slave requires an assembly of two 16-bit Words into a 32-bit Dword The PCEB contains EISA data swap

buffers to support data size translations on the EISA Bus The operation of the data swap logic is described in

the PCEB data sheet The ESC controls the operation of the PCEB’s data swap logic with the following PCEB

ESC interface signals These signals are outputs from the ESC and inputs to the PCEB

SDCPYEN 130301

SDCPYUP

SDOE 20

SDLE 30

Copy Enable Outputs (SDCPYEN 1331

)

These signals enable the byte copy operations between data byte lanes 0 1 2 and 3 as shown in the Table

ISA master cycles do not perform assemblydisassembly operations

Thus

these cycles use

SDCPYEN 130301

to perform the byte routing and byte copying between lanes EISA master cycles

however can have assemblydisassembly operations These cycles use SDCPYEN 130301

in conjunc-

tion with SDCPYUP and SDLE 30

178

82374EB Datasheet(PDF) 178 Page - Intel Corporation