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82374EB Datasheet(PDF) 181 Page - Intel Corporation |
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82374EB Datasheet(HTML) 181 Page - Intel Corporation |
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181 / 208 page  82374EB82374SB 290476 – 88 Figure 28 EISA Address Buffers Table 37 EISA Address Buffer Control Function Signal Cycle Type EISA Master ISA Master DMA Refresh SALE Pulses Low Pulses Pulses LASAOE Low High Low Low SALAOE High Low High High 122 Coprocessor Interface The numeric coprocessor interface is designed to support PCAT compatible numeric coprocessor exception handling The EISA Clock Divider configuration register bit 5 needs to be set toa1in order to enable the coprocessor error support in the ESC The coprocessor interface consists of FERR signal and IGNNE signal The FERR signal and IGNNE signals are connected directly to the Floating Point Error pin and Ignore Floating Point Error pin of the CPU respectively Whenever an error during computation is detected the CPU asserts the FERR signal to the ESC The ESC internally generates an interrupt on the IRQ13 line of the integrated Interrupt Controller The result is a asserted INTR signal to the CPU 181 |
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