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82374EB Datasheet(PDF) 180 Page - Intel Corporation |
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82374EB Datasheet(HTML) 180 Page - Intel Corporation |
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180 / 208 page ![]() 82374EB82374SB 120 INTEGRATED SUPPORT LOGIC The ESC integrates support logic for assorted functions for a typical EISA system board The following func- tions are directly supported by the ESC EISA Address Buffer Control Coprocessor Interface BIOS Interface Keyboard Controller Interface Real Time Clock Interface Floppy Disk Controller Interface Configuration RAM Interface X-Bus and IDE Decode NOTE The ESC directly supports X-Bus Floppy Disk Controller and IDE If the IDE resides on another bus (eg ISA or PCI Bus) additional hardware (to modify the X-Bus signals) is required to support the X-Bus Floppy Disk Controller 121 EISA Address Buffer Control The EISA Bus consists of unlatched addresses (LA 312 ) and latched addresses (SA 192 ) EISA devices generate or monitor LA addresses and ISA devices generate or monitor SA addresses Three Discrete F543s are used to generate the SA address from LA and LA addresses from SA addresses (Figure 28) The ESC generates the control signals SALE LASAOE and SALAOE for the F543s These signals control the direction of the address flow For EISA master DMA and Refresh cycles the the LA addresses are generated by the master device and the SA addresses are driven by the F543s For ISA master devices the SA addresses are generated by the master device and the LA addresses by driven by the F543s 180 |
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