AN2381 datasheet(27/47 Pages) STMICROELECTRONICS

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AN2381

Registers Description

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is performed until both upper and lower part of OUTX register are read. XOR is cleared

anytime OUTX_H register is read.

The ZYXDA bit signals that a new sample for all the enabled channels is available. ZYXDA

is cleared when the Most Significant part of all the enabled channels are read.

ZDA is set to 1 whenever a new acceleration sample related to the Z-axis is available. ZDA

is cleared anytime OUTZ_H register is read. In order to trigger, the ZDA bit requires the Z

axis to be enabled (bit Zen=1 inside CTRL_REG1).

YDA is set to 1 whenever a new acceleration sample related to the Y-axis is available. YDA

is cleared anytime OUTY_H register is read. In order to trigger, the YDA bit requires the Y

axis to be enabled (bit Yen=1 inside CTRL_REG1).

XDA is set to 1 whenever a new acceleration sample related to the X-axis is available. XDA

is cleared anytime OUTX_H register is read. In order to trigger, the XDA bit requires the X

axis to be enabled (bit Xen=1 inside CTRL_REG1).

5.3.3

OUTX_L (28h)

X-axis output register, less significant bits.

In Big Endian Mode (bit BLE in CTRL_REG2 set to ‘1’) the content of this register becomes

the Most Significant part of acceleration data and depends by bit DAS in CTRL_REG2

5.3.4

OUTX_H (29h)

X-axis output register, most significant bits.

When reading the register in “12 bit right justified” mode (bit DAS in CTRL_REG2 register

set to 0) the most significant bits (7:4) are replaced with XD11 (i.e. XD15-XD12=XD11,

XD11, XD11, XD11).

In Big Endian Mode (bit BLE in CTRL_REG2 set to ‘1’) the content of this register becomes

the Less Significant part of acceleration data.

5.3.5

OUTY_L (2Ah)

Y-axis output register, less significant bits.

XD7

XD6

XD5

XD4

XD3

XD2

XD1

XD0

XD7, XD0

X axis acceleration data LSb (bit BLE in CTRL_REG2 register set to ‘0’)

XD15

XD14

XD13

XD12

XD11

XD10

XD9

XD8

XD15, XD8

X axis acceleration data MSb (bit BLE in CTRL_REG2 register set to ‘0’)

YD7

YD6

YD5

YD4

YD3

YD2

YD1

YD0

YD11, YD8

Y axis acceleration data LSb (bit BLE in CTRL_REG2 register set to ‘0’)

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