AN2381 datasheet(31/47 Pages) STMICROELECTRONICS

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AN2381

Registers Description

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This register keeps track of the acceleration event which is being triggering (or has

triggered, in case of LIR bit in FF_WU_SRC reg set to 1) the interrupt signal. In particular IA

is equal to 1 when the combination of acceleration events specified in FF_WU_CFG register

is true. This bit is used for the generation of the interrupt signal associated to the free-

fall/wake-up events (see Figure 17 for any additional detail).

X, (Y, Z) high is true when the module of the acceleration value of the X (Y, Z) channel is

higher than the preset threshold which is defined as the concatenation of FF_WU_THS_H &

FF_WU_THS_L.

Similarly, X, (Y, Z) low is true when the module of the acceleration value of the X (Y, Z)

channel is lower than FF_WU_THS_H & FF_WU_THS_L. Refer to Figure 12 for more

details.

5.4.4

FF_WU_ACK (32h)

Dummy register. A read at this address clears the FF_WU_SRC reg and the FF, WU

interrupt if the latched option was chosen (LIR bit in FF_WU_CFG reg set to 1).

5.4.5

FF_WU_THS_L (34h)

Free-Fall, Wake-Up threshold, less significant bits.

5.4.6

FF_WU_THS_H (35h)

Free-Fall, Wake-Up threshold, most significant bits.

FF_WU_THS_H and FF_WU_THS_L registers define the threshold which is used by the

system to detect any free-fall or inertial wake-up event. The threshold value is expressed

over 16 bit as an unsigned number. In particular 7FFFh corresponds to full-scale

acceleration (i.e. either 2g or 6g depending on the value of FS bit in CTRL_REG2).

5.4.7

FF_WU_DURATION (36h)

Set the minimum duration of the free-fall/wake-up event that must be recognized by the

LIS3LV02DL

THS7

THS6

THS5

THS4

THS3

THS2

THS1

THS0

THS7, THS0

Free-fall / wake-up Threshold Lsb

THS15

THS14

THS13

THS12

THS11

THS10

THS9

THS8

THS15, THS8

Free-fall / wake-up Threshold Msb

FWD7

FWD6

FWD5

FWD4

FWD3

FWD2

FWD1

FWD0

FWD7, FWD0

Free-fall / wake-up minimum duration threshold

(default value 00h)

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