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AN2381 Datasheet(PDF) 39 Page - STMicroelectronics |
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AN2381 Datasheet(HTML) 39 Page - STMicroelectronics |
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39 / 47 page  AN2381 Application information 39/47 6.4 Interrupt generation description The LIS3LV02DL can provide an interrupt signal and offers several possibilities to personalize this signal. The registers involved in the interrupt generation behavior are CTRL_REG2, FF_WU_CFG, FF_WU_THS, FF_WU_DURATION, DD_CFG, DD_THSI, DD_THSE. In this section a brief description of the capability of the interrupt generation is provided. The LIS3LV02DL interrupt signal can behave as Free-Fall, Wake-Up and/or Direction Detector. Whenever an interrupt condition is verified the interrupt signal goes high and reading FF_WU_SRC and DD_SRC registers it is possible to understand which condition happened. Free-Fall signal (FF) and Wake-Up signal (WU) interrupt generation block is represented by the diagram below: Figure 14. Free-Fall, Wake-Up Interrupt Generator FF or WU interrupt generation is selected through AOI bit in FF_WU_CFG register (address 30 hexadecimal). If AOI bit is ‘0’ signals coming from comparators are put in logical or. Depending on values written in FF_WU_CFG register every time the value of almost one of the enabled axes exceeds the threshold written in module in FF_WU_THS registers a FF, WU interrupt is generated. Otherwise if AOI bit is ‘1’ signals coming from comparators are going into a “NAND” port. In this case an interrupt signal is generated only if all the enabled axes are passing the threshold written in FF_WU_THS registers. Table 6. Output Data Registers Content vs. Acceleration (FS= 2g) Acceleration Values DAS=0; BLE=0 DAS=0; BLE=1 DAS=1; BLE=0 DAS=1; BLE=1 Register Address 28h 29h 28h 29h 28h 29h 28h 29h 0 g 00h 00h 00h 00h 0xh 00h 00h 0xh 350 mg 66h 01h 01h 66h 6xh 16h 16h 6xh 1 g 00h 04h 04h 00h 0xh 40h 40h 0xh -350 mg 9Ah FEh FEh 9Ah Axh E9h E9h Axh -1g 00h FCh FCh 00h 0xh C0h C0h 0xh THS reg |b|>a? |b|>a? |b|>a? Accel_X Accel_Y Accel_Z X_en Y_en Z_en WU FF 0 1 FF_WU_CFG(AOI) |
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