AN2381 datasheet(40/47 Pages) STMICROELECTRONICS

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Application information

AN2381

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FF_WU_CFG(LIR) bit permits to decide if the interrupt request has to be latched or not. If

LIR bit is ‘0’ (default value) interrupt signal goes high when the interrupt condition is satisfied

and comes back low immediately if the interrupt condition is no more verified. Otherwise if

LIR bit is ‘1’ whenever a interrupt condition is applied the interrupt signal remains high even

if the condition comes back to non-interrupt status until a reading to FF_WU_ACK register is

performed.

The remaining bits of FF_WU_CFG register permits to decide on which axis the interrupt

decision has to be performed and on which direction the threshold has to be passed to

generate the interrupt request.

Figure 15 is a representation of Direction Detector Interrupt Generator for one of the axes.

The data coming from comparators are compared with the one of the previous acquisition. If

a difference is found it means that the threshold written in the DD_THS registers was

exceeded and an interrupt signal is generated. If different values are used for DD_THSE

and DD_THSI registers it is possible to introduce an hysteresis in the interrupt generation.

The difference between WU and DD signals is that the first one gives information if the

device reads statically an acceleration in a chosen range while the second one provides an

information on the device movement from a position. Reading Direction Detector Source

movement has happened.

Figure 15.

Direction Detector Interrupt Generator for X axis

These Interrupt generator blocks can be combined with the embedded High Pass filter in

order to obtain further feature.

Furthermore, as described in Figure 17, FF_WU and DD can be used together to generate

an interrupt signal that is the logic "OR" of the two interrupts.

b>a?

b<-a?

|b|<a?

DD_THSEreg

DD_THSI reg

Accel_X

Memory

cell

Memory

cell

XH_en

XL_en

AN2381 Datasheet(PDF) 40 Page - STMicroelectronics