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UPD70732 Datasheet(PDF) 21 Page - NEC |
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UPD70732 Datasheet(HTML) 21 Page - NEC |
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21 / 66 page ![]() 21 µPD70732 5. BUS INTERFACE FUNCTION The V810 is equipped with a 32-bit data bus. In the bus interface, there are two modes: 32-bit bus mode which uses the data bus in 32 bits and 16-bit bus fixed mode which fixes the bus in 16 bits. Modes can be switched only at reset using the SIZ16B signal. The 32-bit bus mode has a dynamic bus sizing function which uses the data bus in 16-bit bus width to access the 16-bit peripherals. This function can be used by setting the SZRQ signal active. Access to word data (32-bit data) in the dynamic bus sizing is executed by loading/storing a 16-bit data twice. In the 16-bit bus fixed mode, access to word data (32-bit data) is executed by activating a bus cycle twice. The control signal and the A1 signal output values according to the 16-bit system. The relationship between the external access and byte enable signals (BE3 to BE0) during the 32-bit bus mode and the 16-bit bus fixed mode is shown below. Table 5-1. Relationship among Address, Data Length, Byte Enable Signals and A1 (32-bit bus mode) Operand address Byte enable Bit 1 Bit 0 BE3 BE2 BE1 BE0 Byte 0 0 1 1 1 0 0 1 011 101 0 1 101 011 0 1 110 111 0 1 Halfword 0 0 1 1 0 0 0 1 100 011 0 1 Word 0 0 0 0 0 0 0 1 0 011 1 2Note Note Bus cycle added by dynamic bus sizing Table 5-2. Relationship among Address, Data Length, Byte Enable Signals and A1 (16-bit bus fixed mode) Operand address Byte enable Bit 1 Bit 0 BE3 BE2 BE1 BE0 Byte 0 0 Hi-Z Hi-Z 1 0 0 1 0 1 Hi-Z Hi-Z 0 1 0 1 1 0 Hi-Z Hi-Z 1 0 1 1 1 1 Hi-Z Hi-Z 0 1 1 1 Halfword 0 0 Hi-Z Hi-Z 0 0 0 1 1 0 Hi-Z Hi-Z 0 0 1 1 Word 0 0 Hi-Z Hi-Z 0 0 0 1 Hi-Z Hi-Z 0 0 1 2Note Note Added bus cycle Data length A1 Bus cycle sequence Data length A1 Bus cycle sequence 5 |
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