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UPD70732 Datasheet(PDF) 23 Page - NEC |
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UPD70732 Datasheet(HTML) 23 Page - NEC |
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23 / 66 page ![]() 23 µPD70732 7. CACHE Figure 7-1 shows the instruction cache configuration provided to the V810. Figure 7-1. Cache Configuration Capacity : 1 Kbytes Mapping system : direct map Block size : 8 bytes Sub-block size : 4 bytes 5 31 27 22 31 0 0 21 10 Memory address TAG TAG31 to TAG10 Tag memory (ICHT27 to ICHT0) Data memory (ICHD31 to ICHD0) Entry 0 Entry 1 128 entries Entry 127 Valid bits (1 bit for every 4 bytes) NECRV (Reserved by NEC) Sub-block (4 bytes) Block (8 bytes) Offset Index 93 2 0 128 blocks |
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