UM0851 datasheet(163/245 Pages) STMICROELECTRONICS

163 / 245 page

UM0851

Accelerator engine device drivers

Doc ID 16604 Rev 2

163/245

Figure 42.

DMAC block diagram

The SPEAr family uses the ARM PL080 DMA controller, which is connected to the AHB bus.

Its main features are:

●

Eight DMA channels. Each channel can support a unidirectional transfer.

●

16 DMA requests. The DMAC provides 16 peripheral DMA request lines.

●

Single DMA and burst DMA request signals. Each peripheral connected to the DMAC

can assert either a burst DMA request or a single DMA request. You set the DMA burst

size by programming the DMAC.

●

Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-

peripheral transfers.

●

Scatter or gather DMA support through the use of linked lists.

●

Hardware DMA channel priority. Each DMA channel has a specific hardware priority.

DMA channel 0 has the highest priority and channel 7 has the lowest priority. If

Channel0

Channel1

DMA request

and response

block

AHB slave

interface

Channel7

AHB bus

AHB Master 1

AHB Master 2

AHB

Mast.

I/F

AHB

Mast.

I/F

DMACCLR[15:0]

DMACTC[15:0]

DMACSREQ[15:0]

DMACBREQ[15:0]

DMACLSREQ[15:0]

DMACLBREQ[15:0]

UM0851 Datasheet(PDF) 163 Page - STMicroelectronics

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