UM0851 datasheet(166/245 Pages) STMICROELECTRONICS

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Accelerator engine device drivers

UM0851

166/245

Doc ID 16604 Rev 2

DMA transfer configuration

There are four types of DMA transfer possible: memory-set, memory-to-memory, peripheral-

to-peripheral and memory-to/from-peripheral. The first two can work either with the default

configuration of the DMA driver or the configuration provided by client. Transfers with

peripherals always require the user to pass the configuration.

Configuration parameters are passed to the DMA driver using the struct dma_slave *slave

pointer present in struct dma_client.

/* We need to pass address of transmit register in tx_reg and receive register in

rx_reg for DMA_SLAVE transfers, otherwise this structure must not be

filled by

user driver.

Note: Address of this slave structure has to be passed to in slave pointer in

client structure. */

struct dw_dma_slave {

struct dma_slave

slave;

/* Generic information about the slave. See

below */

u32

ctl;

/* Platform-specific value for the CTL

information include

src/dest access width, src/dest

burst size,

dmac modes, interrupt option after each

packet transfer, src/dest address increment

after each access_width sized transfer. Please

see

<linux/spr_dmac_pl080.h> for further

information. */

u32

cfg;

/* Platform-specific value for the CFG register.

Configuration information include transfer flow

controller and

src/dest request id (physical

request line between peripheral and DMAC),. Please

see <linux/spr_dmac_pl080.h> for further

information.*/

enum dma_master src_master;

/* DMA masters for source and destination side.

Masters are fixed for the board architecture.

Master information is

present in enum

dma_master_info present in <mach/dma.h>. */

enum dma_master dest_master;

void

*private_data;

/* It is for client driver private data

purposes. It can be extracted from pointer to

client structure in dma_event callback. */

};

/* Generic information about the slave. See below */

struct dma_slave {

struct device

*dev;

struct device

*dma_dev;

dma_addr_t

tx_reg;

dma_addr_t

rx_reg;

enum dma_slave_widthreg_width;

};

This slave structure must be defined by the client driver before requesting DMA channels. It

must be filled with configuration values before preparing DMA transfer.

The default DMA driver ctl configuration for memory-to-memory transfers is:

DWC_CTL_USER_MODE | DWC_CTL_NON_BUFFERABLE | DWC_CTL_NON_CACHEABLE |

DWC_CTL_DEST_BURST(BURST_8) | DWC_CTL_SRC_BURST(BURST_8) |

DWC_CTL_DEST_WIDTH(width) | DWC_CTL_SRC_WIDTH(width) | DWC_CTL_DEST_ADDR_INC

The default DMA driver ctl configuration for memset transfers is:

UM0851 Datasheet(PDF) 166 Page - STMicroelectronics

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