UM0851 datasheet(216/245 Pages) STMICROELECTRONICS

216 / 245 page

Miscellaneous device drivers

UM0851

216/245

Doc ID 16604 Rev 2

Figure 61 below shows three different PWM signals. Figure 61 (a) shows a PWM output at a

10% duty cycle. That is, the signal is on for 10% of the period and off the other 90%.

Figure 61 (b) and (c), show PWM outputs at 50% and 90% duty cycles, respectively. These

three PWM outputs encode three different analog signal values, at 10%, 50%, and 90% of

the full strength. If, for example, the supply is 9 V and the duty cycle is 10%, a 0.9 V analog

signal results.

Figure 61.

PWM output with (a) 10%, (b) 50% and (c) 90% duty cycle

SPEAr320 contains a PWM IP with four independent channels (PWM1, PWM2, and PWM3,

PWM4). All four channels are functionally identical. Using a 16-bit counter, each PWM

channel generates a rectangular output pulse with programmable duty factor (0 to 100%)

and frequency.

Features of SPEAr320 PWM:

●

Four independent PWM channels

●

Prescaler to define the input clock frequency to each timer

●

Programmable duty factor from 0 to 100%

●

Programmable pulse frequency, or period

●

APB clock (PCLK ~ 83 MHz) as the source clock for prescaler

The relationship of duty to period is described in the following figure:

10%

50%

90%

On = high level, Off = low level

(a)

(b)

(c)

UM0851 Datasheet(PDF) 216 Page - STMicroelectronics