UM0851 datasheet(232/245 Pages) STMICROELECTRONICS

232 / 245 page

Power management section

UM0851

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Doc ID 16604 Rev 2

the Transition Notifier in the CPUfreq core, so that the drivers listed in the CPUfreq

transition notifier lists are informed of the change.

The kernel also provides a notification list in the CPUfreq framework that the device drivers

can register into. This notification list is called as Transition Notifier ( being used in Ethernet

driver for reference). The drivers impacted on CPUfreq change are notified twice when the

CPUfreq driver switches the CPU core frequency and this change has any external

implications on the drivers. The calls are made before and after the frequency change to

allow the drivers to judge the impact of the change.

Device driver perspective

The architecture supports devices which have their clocks (either functional or interface

clocks) running on the same system clock (PLL-1) as the CPU. Below is a list of devices

which could be impacted by a change of frequency and any required actions that are

handled by the drivers.

CLCD

: The current implementation has the CLCD running on PLL-3 and is not

impacted by the change in PLL-1/CPU frequency changes.

Ethernet

: DMA transactions to be stopped momentarily, when the PLL frequency

change is taking place. Also the MDIO clock needs to be programmed properly after

the frequency change. The IP reads the clock rate from the Clock Framework.

USB Host/Device

: DMA transactions would be suspended and then resumed as done

in Ethernet.

I2C

: Before any transaction takes place, I2C driver will fetch the functional clock rate

from the clock framework, and then program its internal register with the necessary

SCL clock values. It will also Enable and Disable the i2c clock as per its requirement.

UART

: Will always transmit/receive post reading the clock rate from the clock

framework, and hence will not depend directly on the CPU Freq changes. It will enable

and disable the clocks as per the read/write requirements.

GPT

: Will setup the events post reading the clock rate from the clock framework, and

hence will not directly depend on the CPU freq changes. The system timer would be

running on PLL-3, so as to avoid the changes in PLL affecting the timer interrupts.

SPI

: Will run fine as long as minimum clock speed is maintained.

SMI

: Will run fine as long as minimum clock speed is maintained.

FSMC

: Will run fine as long as minimum clock speed is maintained.

10. JPEG: No impact

11. WDT: No impact

12. DMA: Disable the individual channels momentarily when the PLL frequency change

over takes place, and then resume them as soon as PLL is locked. Make sure that the

data present in FIFO's have been flushed. The user manual provides the details for

handling the same.

13. ADC: Driver would reprogram its internal registers based on the new clock rate every

time by calling into clk_get_rate().

14. DDR: If the DDR is running on PLL-2, then there is no impact of the PLL-1 frequency

change, but if the DDR is running on PLL-1, then the DDR should be put in Self-

Refresh Mode and then the PLL-1 frequency would be changed and then the DDR

would be moved to normal mode.

In the current implementation, DDR should be running on PLL-2 only

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