UM1865 datasheet(126/132 Pages) STMICROELECTRONICS

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SPI interface

UM1865

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SPI interface

The BlueNRG-MS device provides an SPI interface, which can be used to connect an

external device. The external device normally is an application processor. It sends ACI

commands to control the BlueNRG-MS device. And the BlueNRG-MS generates ACI events

to report back to the external application processor. The ACI commands and events are

transmitted through the SPI bus.

This chapter describes the BlueNRG-MS hardware SPI interface. Also it describes the

communication protocol over the SPI bus between the BlueNRG-MS and the external

device.

5.1

Hardware SPI interface

The BlueNRG-MS SPI interface is Motorola protocol compliant, which has 5 wires: CLK

(clock), nCS (chip select), MOSI (master output slave input), MISO (master input slave

output), and DataRdy_IRQ (transmit interrupt request).

The BlueNRG-MS always behaves as the slave device on the SPI bus. The external device

must be the SPI master.

The table below shows the 5 SPI pins on the BlueNRG-MS device, including the pin number

of the silicon chip and the pin direction from the BlueNRG-MS's side.

Here is the summary of the SPI parameters:

The CS line is active low.

The clock signal can go up to 8 MHz, or can go as low as 100 kHz.

The clock is inactive low, i.e. the clock polarity CPOL = 0.

The data is valid on clock leading edge, i.e. the clock phase CPHA = 0.

The data transfer is always 8-bit byte based.

For each byte, the Most Significant Bit is sent first.

Figure 9 shows how to connect BlueNRG-MS SPI bus to an external SPI master.

Table 297. SPI pins

Pin name

Pin n°

Direction

SPI_CLK

Input

SPI_NCS

Input

SPI_MOSI

Input

SPI_MISO

Output

SPI_IRQ

Output

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